Patents by Inventor George Van Horn Leming, III

George Van Horn Leming, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11822487
    Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: November 21, 2023
    Assignee: Ampere Computing LLC
    Inventors: George Van Horn Leming, III, John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Bret Leslie Toll
  • Patent number: 11386016
    Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Ampere Computing LLC
    Inventors: George Van Horn Leming, III, John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Bret Leslie Toll
  • Publication number: 20220091997
    Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: George Van Horn Leming, III, John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Bret Leslie Toll
  • Publication number: 20210191877
    Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: George Van Horn Leming, III, John Gregory Favor, Stephan Jean Jourdan, Jonathan Christopher Perry, Bret Leslie Toll