Patents by Inventor George Vergis

George Vergis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294167
    Abstract: A connector includes connector pins that have a loop of conductor. The connector connects a first printed circuit board (PCB) to a second PCB with compression of the connector pins between the two boards. In response to compression of the connector, the connector pins make electrical contact with themselves through the loop, while also connecting pads of the first PCB to pads of the second PCB.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Xiang Li, Konika Ganguly, George Vergis
  • Publication number: 20250126714
    Abstract: Memory modules and sockets are disclosed. An example memory module comprises a circuit board, a first row of connection pins disposed along an edge of the circuit board, and a second row of pins disposed adjacent to the first row of pins and further from the edge than the first row of pins.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Xiang Li, Todd Hinck, George Vergis, James McCall
  • Patent number: 12267957
    Abstract: Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Xiang Li, George Vergis, Jeffrey Krieger
  • Publication number: 20250071924
    Abstract: Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Intel Corporation
    Inventors: Phil Geng, David Shia, Xiang Li, George Vergis, Ralph Miele, Sanjoy Saha, Jeffory Smalley
  • Patent number: 12237620
    Abstract: Examples described herein relate to a pin arrangement that includes a first signal pin; a second signal pin; and multiple parallel ground pins positioned between the first and second signal pins. In some examples, the multiple parallel ground pins are coupled to a single pin connector coupled to a first device and a single pin connector coupled to a second device. In some examples, a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin and wherein a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin. In some examples, the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Xiang Li, George Vergis
  • Patent number: 12147698
    Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Bill Nale, George Vergis
  • Patent number: 12144110
    Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Guixiang Tan, Xiang Li, Casey Winkel, George Vergis
  • Patent number: 12106818
    Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Aiswarya M. Pious, Raji James, Phani K. Alaparthi, George Vergis, Bill Nale, Konika Ganguly
  • Patent number: 12087352
    Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: September 10, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
  • Patent number: 12069329
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: August 20, 2024
    Assignee: Universal Electronics Inc.
    Inventors: George Vergis, Sunilkumar Mankame
  • Patent number: 12040568
    Abstract: Connectors with a staggered pin orientation can reduce crosstalk amongst signal pins. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. Each of the plurality of pins includes two ends including a card or module-facing end to couple with the card or module and a motherboard-facing end to couple with the motherboard. Each of the plurality of pins includes a middle section in the connector housing. One or both of the ends include one or more bends relative to the middle section. The plurality of pins includes alternating signal pins and ground pins, wherein the signal pins having an opposite orientation relative to the ground pins.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: July 16, 2024
    Assignee: Intel Corporation
    Inventors: Xiang Li, Konika Ganguly, George Vergis
  • Patent number: 11984685
    Abstract: An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Phil Geng, Xiang Li, George Vergis, Mani Prakash
  • Patent number: 11961391
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 16, 2024
    Assignee: Universal Electronics Inc.
    Inventor: George Vergis
  • Patent number: 11928042
    Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Dat T. Le, George Vergis
  • Patent number: 11921652
    Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Amit Kumar Srivastava, George Vergis
  • Publication number: 20230421832
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 28, 2023
    Inventors: George Vergis, Sunlikumar Mankame
  • Patent number: 11789880
    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: October 17, 2023
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Emily P. Chung, Frank T. Hady, George Vergis
  • Patent number: 11792466
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: October 17, 2023
    Assignee: Universal Electronics Inc.
    Inventors: George Vergis, Sunilkumar Mankame
  • Patent number: 11776619
    Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: October 3, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Chong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
  • Publication number: 20230252886
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventor: George Vergis