Patents by Inventor George W. Daly
George W. Daly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9710310Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: August 17, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Patent number: 9606838Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: August 17, 2015Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Patent number: 9251077Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.Type: GrantFiled: September 25, 2013Date of Patent: February 2, 2016Inventors: Bartholomew Blaner, David W. Cummings, George W. Daly, Jr., Michael S. Siegel, Jeff A. Stuecheli
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Publication number: 20150355949Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, JR., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Publication number: 20150355948Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Patent number: 8990513Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.Type: GrantFiled: January 11, 2013Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, David W. Cummings, George W. Daly, Jr., Michael S. Siegel, Jeff A. Stuecheli
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Publication number: 20140201465Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.Type: ApplicationFiled: September 25, 2013Publication date: July 17, 2014Inventors: Bartholomew Blaner, David W. Cummings, George W. Daly, JR., Michael S. Siegel, Jeff A. Stuecheli
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Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
Patent number: 7788423Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.Type: GrantFiled: August 6, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: George W. Daly, Jr., James S. Fields, Jr. -
Patent number: 7725619Abstract: A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.Type: GrantFiled: September 15, 2005Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: George W. Daly, Jr., James S. Fields, Jr., Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli
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Patent number: 7568060Abstract: A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.Type: GrantFiled: December 15, 2005Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: George W. Daly, Jr., James S. Fields, Jr., Donald G. Grice, Thomas J. Heller, Appoloniel N. Tankeh
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Patent number: 7562171Abstract: A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.Type: GrantFiled: September 12, 2007Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: George W. Daly, Jr., James S. Fields, Jr., Donald G. Grice, Thomas K. Heller, Jr., Appoloniel N. Tankeh
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Method and Apparatus for Invalidating Cache Lines During Direct Memory Access (DMA) Write Operations
Publication number: 20080294807Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.Type: ApplicationFiled: August 6, 2008Publication date: November 27, 2008Applicant: IBM CORPORATIONInventors: George W. Daly, JR., James S. Fields, JR. -
Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
Patent number: 7451248Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.Type: GrantFiled: February 9, 2005Date of Patent: November 11, 2008Assignee: International Business Machines CorporationInventors: George W. Daly, Jr., James S. Fields, Jr. -
Patent number: 7308557Abstract: A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.Type: GrantFiled: February 9, 2005Date of Patent: December 11, 2007Assignee: International Business Machines CorporationInventors: Richard L. Arndt, George W. Daly, Jr., James S. Fields, Jr., Warren E. Maule
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Patent number: 6687795Abstract: A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.Type: GrantFiled: December 20, 2000Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, George W. Daly, Jr., Paul Umbarger
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Publication number: 20020124145Abstract: A data processing system includes a plurality of snoopers coupled to an interconnect. In response to a memory access request transmitted on an interconnect by one of the snoopers receiving a Retry response, a determination is made whether or not the Retry response was caused by a target snooper that will service the memory access request. If not, the target snooper services the memory access request in spite of the Retry response. In a preferred embodiment in which the memory access request is a write request and the target snooper is a memory controller, stale data cached by at least one snooper in association with the address are also invalidated by a snooper, such as the memory controller, transmitting at least one address-only kill transaction on the interconnect. Advantageously, the address-only kill transaction can be issued concurrently with or following servicing the write request so that the write request does not incur latency by waiting until all stale copies of the data have been invalidated.Type: ApplicationFiled: December 20, 2000Publication date: September 5, 2002Applicant: International Business Machines CorporationInventors: Ravi Kumar Arimilli, George W. Daly, Paul Umbarger
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Patent number: 4151971Abstract: A device for mounting a speaker cabinet to various structural supports such as a wall, ceiling, floor or corner is disclosed. The device comprises a strut having two telescoping mutually rotatable members, and means for interlocking the members to fix the length and orientation of the strut. A flange having a plurality of apertures is fixed to one end of the telescopic strut for mounting the strut to the structural support. The configuration of the flange may be adapted to the shape of the structural support. In one embodiment, a flat flange is provided for mounting to planar support surfaces. In another embodiment, the flange includes a central planar portion and opposed inclined portions defining a 90.degree. angle so that the flange can be used to mount the telescoping strut to a corner surface. A bracket is pivotably mounted to the other end of the strut and has a plurality of apertures for mounting to the speaker cabinet.Type: GrantFiled: October 12, 1977Date of Patent: May 1, 1979Assignee: Mastermount CorporationInventors: George W. Daly, Joseph R. Rucker
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Patent number: 4074883Abstract: A device for mounting a speaker cabinet to various structural supports such as a wall, ceiling, floor or corner is disclosed. The device comprises a strut having two telescoping mutually rotatable members, and means for interlocking the members to fix the length and orientation of the strut. A flange having a plurality of apertures is fixed to one end of the telescopic strut for mounting the strut to the structural support. The configuration of the flange may be adapted to the shape of the structural support. In one embodiment, a flat flange is provided for mounting to planar support surfaces. In another embodiment, the flange includes a central planar portion and opposed inclined portions defining a 90.degree. angle so that the flange can be used to mount the telescoping strut to a corner surface. A bracket is pivotably mounted to the other end of the strut and has a plurality of apertures for mounting to the speaker cabinet.Type: GrantFiled: March 31, 1976Date of Patent: February 21, 1978Assignee: Mastermount CorporationInventors: George W. Daly, Joseph R. Rucker