Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.

Abstract: A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.

Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.

Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.

Abstract: A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design platform descriptions provide design information about one or more platforms capable of instantiating the integrated circuit design.

Abstract: An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

Abstract: A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

Abstract: The present invention is directed to a reconfigurable memory controller. A reconfigurable memory controller may include a plurality of communicatively coupled memory controllers. The plurality of communicatively coupled memory controllers is reconfigurable so that the controllers are groupable into a first memory configuration and a second memory configuration. The first memory configuration has a different bandwidth grouping than the second memory configuration.

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

Abstract: An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

Abstract: A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a directory entry identified for a data operation is read into the CAM for the data operation. The directory entry for the data operation in the CAM is locked while the data operation is pending. Other entries in the congruence class are available. When the data operation is completed, checking for a state change is performed. Responsive to an identified state change, the directory entry for the data operation in the CAM is updated or marked as changed. The congruence class including the updated directory entry is marked as dirty. In accordance with features of the invention, the changed congruence class directory entries in the CAM are accumulated and scheduled to be written back to the N-way associative directory.

Abstract: An apparatus and method in a data processing system for sending a data packet from a source node to a destination node. The data processing system includes a multi-segment network having at least two segments, wherein the source node and the destination node are located within different segments. Communication of a data packet from one segment to another segment is provided by an agent node. When a receiving node, which may be either an agent or a destination node, cannot accept a packet, it places a reservation tag of "A" or "B" in an echo packet. The retried packet then uses this reservation tag to gain priority for any available buffers in the agent or destination node. The receiving node toggles between accepting all the outstanding "A" packets (when the receiving node is in the "receiving A" state) and accepting all the outstanding "B" packets (when the receiving node is in the "receiving B" state) assuming that the receiving node has a free, unoccupied buffer for accepting the packet.

Abstract: A ring configurator for interconnection of data processing and communication systems uses fully covered rings. The ring configuration mechanism can be used to construct a set of covering rings preserving full connectivity for system interconnect. The mechanism can also be used for establishing the routing table for each interconnected system during the system initialization time. To generate a set of edge-disjoint rings, a rotational mechanism is used. The rings are considered stretching along a horizontal direction with nodes aligned in columns across all the rings. With a proper relabeling of the nodes, nodes appearing in the same column position of each ring can be obtained by a simple rotation of the nodes from the previous column of the rings. Once the rotational position is determined for each column, a set of N-1 edge-disjoint rings can be constructed. To find an extra ring so that when combined with the N-1 rings thus found the ring constraints are satisfied, a node reduction technique is invoked.

Abstract: The present invention provides a method in a data processing system for efficiently sending a data packet from a source node to a destination node. The data processing system includes a multi-segment network having at least two segments, wherein the source node and the destination node are located within in different segments. Communication of a data packet from one segment to another segment is provided by an agent node. The present invention generates a data packet at the source node within a first segment on the multi-segment network. The data packet includes a source address, a destination address, and data. The data packet is then transmitted within the first segment and the source node retains ownership of the data packet. Thereafter, the data packet is received within the first segment at an agent node. The data packet is examined to determine the destination address and then transmit it to the destination node within a second segment in the multi-segment network.

Abstract: A retry filter and circulating echo apparatus and method are provided for a digital processing system of the type having multiple nodes that communicate via one or more unidirectional rings. The nodes of a digital processing system communicate packets to each other over a unidirectional ring bus. An origination node allocates a sequence identification and transmits a packet to a destination node, which generates a first echo packet and also sets a packet filter indication to drop any further copies of that packet. The first echo packet is sent to the origination node as a confirmation. The origination node generates a second echo packet and sends the generated second echo packet onward to the destination node again as an indication that the packet will not be retransmitted. The destination node transmits a third echo packet as an indication that the sequence can be deallocated.