Abstract: A method is provided for fabricating totally self-aligned contacts on semiconductor substrates. The method is particularly applicable to dynamic random access memory for reducing the cell area. The method involves patterning the silicon nitride layer for the local oxidation of silicon (LOCOS) process to provide wide device areas for the gate electrode of the FETs, and narrow device areas adjacent and contiguous to the wide device areas on and in which are formed portions of the source/drain areas and the totally self-aligned contacts. The lateral encroachment of the field oxide (bird's beak) into the narrow device areas during the LOCOS process reduce the width of the area to about 0.20 um, and thereby extend the resolution limit of the current lithography (about 0.40 um) used to define the nitride layer.