Patents by Inventor George Wiley

George Wiley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10042797
    Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley
  • Patent number: 9880895
    Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley
  • Publication number: 20180006846
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.
    Type: Application
    Filed: May 17, 2017
    Publication date: January 4, 2018
    Inventors: George Wiley, Glenn Raskin, Chulkyu Lee
  • Patent number: 9819523
    Abstract: An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: November 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chulkyu Lee, Shih-Wei Chou, George Wiley
  • Publication number: 20170309167
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.
    Type: Application
    Filed: July 13, 2017
    Publication date: October 26, 2017
    Inventors: George Wiley, Glenn Raskin
  • Publication number: 20170264471
    Abstract: An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 14, 2017
    Inventors: Chulkyu Lee, Shih-Wei Chou, George Wiley
  • Patent number: 9563398
    Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley, Amit Gil
  • Patent number: 9537687
    Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, George Wiley, Richard Wietfeldt, James Panian
  • Publication number: 20160371157
    Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 22, 2016
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley
  • Publication number: 20160259624
    Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 8, 2016
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley, Amit Gil
  • Publication number: 20160224489
    Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 4, 2016
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, George Wiley
  • Publication number: 20160226682
    Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 4, 2016
    Inventors: Lalan Jee Mishra, George Wiley, Richard Wietfeldt, James Panian
  • Patent number: 8848810
    Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Chulkyul Lee, Anosh Davierwalla, George Wiley
  • Patent number: 8496547
    Abstract: A collapsible goal post includes a lower support extending from a playing field; a upper support having a first end and a second end, and a pivot assembly attaching the first end of the upper support to the lower support; an upper assembly comprising two uprights and a crossbar having two ends. The crossbar is attached to the second end of the support at about the midpoint of the crossbar. One of the two uprights is attached to each end of the crossbar. The upper support is configured to pivot about the pivot point assembly to move the upright assembly from a raised position to a lowered position. The two uprights are substantially perpendicular to the playing field in the raised position, and are substantially parallel to and contacting the playing field in the lowered position while the upper assembly and upper support remain attached to the lower support.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: July 30, 2013
    Inventor: George Wiley
  • Patent number: 8364857
    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: January 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: James Pyers, George Wiley, James J. Willkie, Brian Steele, Apul Nahata, Karthik Raj Kaliannan
  • Publication number: 20120142457
    Abstract: A collapsible goal post includes a lower support extending from a playing field; a upper support having a first end and a second end, and a pivot assembly attaching the first end of the upper support to the lower support; an upper assembly comprising two uprights and a crossbar having two ends. The crossbar is attached to the second end of the support at about the midpoint of the crossbar. One of the two uprights is attached to each end of the crossbar. The upper support is configured to pivot about the pivot point assembly to move the upright assembly from a raised position to a lowered position. The two uprights are substantially perpendicular to the playing field in the raised position, and are substantially parallel to and contacting the playing field in the lowered position while the upper assembly and upper support remain attached to the lower support.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 7, 2012
    Inventor: George Wiley
  • Publication number: 20110055434
    Abstract: A computing device includes a low power auxiliary processor, such as a processor on a wireless card or sub-system, which is able to takeover processing in place of the computing device's central processing unit (CPU). Operating the computing device on the auxiliary processor draws less power from the computing device battery, enabling extended operation in an auxiliary processor mode. When in this mode, the auxiliary processor controls peripherals and provides the system functionality while the CPU is deactivated, such as in “off,” “standby” or “sleep” modes. In the auxiliary processor mode, the computing device can accomplish useful tasks, such as sending/receiving electronic mail, displaying electronic documents and accessing a network while drawing minimal power from the battery. Transitions between the normal operating mode and auxiliary processor mode may be transparent to users. Such a computer may display instant on, always on and always connected operating features.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Inventors: James PYERS, George WILEY, James J. WILLKIE, Brian STEELE, Apul NAHATA, Karthik Raj KALIANNAN
  • Publication number: 20090225873
    Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 10, 2009
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chulkyu Lee, Anosh Davierwalla, George Wiley
  • Publication number: 20080088492
    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.
    Type: Application
    Filed: November 9, 2007
    Publication date: April 17, 2008
    Applicant: Qualcomm Incorporated
    Inventors: George Wiley, Brian Steele, Curtis Musfeldt
  • Publication number: 20060288133
    Abstract: The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.
    Type: Application
    Filed: November 23, 2005
    Publication date: December 21, 2006
    Inventors: Behnam Katibian, George Wiley, Brian Steele