Abstract: In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

Abstract: In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

Abstract: UV detectors comprising undoped Zn1-xMgxS as the UV responsive active material. Where x exceeds 0.3 the thickness of the active material must be below a critical value, for example if 0.30<x<1.00, and the active material is formed as a layer of a thickness t wherein 5000 Å≧t≧100 Å. A particularly preferred combination of x and thickness is x=0.57 and t≦1400 Å because at around these values the UV response of the active material is similar to the UV response of human skin.

Abstract: This invention provides a convenient process for preparing an oral contraceptive liquid formulation having improved solubility, bioavailability and stability useful as a reference standard.

Abstract: This invention provides a convenient process for preparing an oral contraceptive liquid formulation having improved solubility, bioavailability and stability useful as a reference standard.

Abstract: A method for making a planar spin-on-glass (SOG) layer over integrated circuits at the corners of the chip (die) areas is achieved. This method allows more reliable integrated circuits to be made, and is particularly useful for liquid crystal displays (LCDs) by eliminating optical distortion at the corners of the LCD die areas. When a conducting layer is patterned to form portions of the integrated circuits over the chip areas, the layer is concurrently patterned to form a fill layer in the kerf areas. The spacing between the fill layer in the kerf areas and the edges of the patterned conducting layer in the die areas is selected to have a width sufficiently narrow to provide a uniform coating of SOG over the corners of the die areas without buildup of the SOG. After depositing a thin SiOx cap layer, a uniform SOG layer is deposited. The fill layer in the kerf areas also prevents dishing of the SOG layer when the SOG is chem-mech polished back.

Abstract: A method for making a planar spin-on-glass (SOG) layer over integrated circuits at the corners of the chip (die) areas is achieved. This method allows more reliable integrated circuits to be made, and is particularly useful for liquid crystal displays (LCDs) by eliminating optical distortion at the corners of the LCD die areas. When a conducting layer is patterned to form portions of the integrated circuits over the chip areas, the layer is concurrently patterned to form a fill layer in the kerf areas. The spacing between the fill layer in the kerf areas and the edges of the patterned conducting layer in the die areas is selected to have a width sufficiently narrow to provide a uniform coating of SOG over the corners of the die areas without buildup of the SOG. After depositing a thin SiOx cap layer, a uniform SOG layer is deposited. The fill layer in the kerf areas also prevents dishing of the SOG layer when the SOG is chem-mech polished back.

Abstract: A process for fabricating pixels and bonding pads wherein each has an optimal metal thickness in the fabrication of a LCD integrated circuit device is achieved. Semiconductor device structures are formed in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A first metal layer is deposited overlying the insulating layer and patterned to form a metal line and a bonding pad. A dielectric layer is deposited overlying the metal line and the bonding pad. Vias are opened through the dielectric layer to the metal line but not to the bonding pad. A second metal layer is deposited overlying the dielectric layer and filling the via openings and etched back to form metal plugs. A third metal layer is deposited overlying the dielectric layer and metal plugs and patterned to form pixels contacting metal plugs. A passivation layer is deposited overlying the pixels. A via opening is etched through the passivation layer and the dielectric layer to the bonding pad.

Abstract: A programmable halogen lamp assembly radiantly heats a post-etch wafer in a semiconductor wafer processing environment to evolve corrosive, chlorine based compounds that reside on or in the processed wafer, preferably during wafer unloading to minimize throughput loss, and preferably under vacuum to prevent the onset of a corrosion reaction.

Abstract: A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate.

Abstract: A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate.

Abstract: A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer has substantially the same grain size as the first aluminum.

Abstract: A new method of metallization of an integrated circuit is described. Semiconductor device structures are fabricated in and on a semiconductor substrate. At least one contact opening to the semiconductor substrate and at least one lithography alignment cross mark opening structure are formed. A barrier layer is preferably sputtered within the contact openings and over the semiconductor device structures. A cold aluminum seed layer is sputtered over all surfaces of the contact openings. Next, a hot aluminum flow layer is provided to obtain the desired step coverage of the contact openings. A second cold aluminum layer is then sputtered onto the hot aluminum layer to define the edges of the wide lithography alignment marks while maintaining good contact opening coverage.

Abstract: The method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer having substantially the same grain size as the first aluminum.

Abstract: A synchronizer for synchronizing a slave tape recorder to a master tape recorder. When the speed of the master recorder exceeds 2.5 times the nominal play speed, the synchronizer causes the slave recorder to lag behind the master recorder by an amount related to the speed of the slave recorder. At lower speeds, the synchronizer causes the slave recorder to lock onto the position and speed of the master recorder. The synchronizer employs time-code readers to read time-code on address tracks on the master and slave recorders. The time-code readers produce not only time-code but also clock pulses which are employed to determine the speed of master and slave with high resolution. Both the time-code readers and a resolver employed in the synchronizer are constructed from gate assemblies rather than processors to reduce execution times for the processor in the synchronizer.