Patents by Inventor George Zacharias

George Zacharias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230143375
    Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 11, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Ishwar AGARWAL, George Zacharias CHRYSOS, Oscar ROSELL MARTINEZ
  • Patent number: 11599415
    Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 7, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Publication number: 20230020131
    Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 19, 2023
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Publication number: 20220414001
    Abstract: Techniques of memory inclusivity management are disclosed herein. One example technique includes receiving a request from a core of the CPU to write a block of data corresponding to a first cacheline to a swap buffer at a memory. In response to the request, the method can include retrieving metadata corresponding to the first cacheline that includes a bit encoding a status value indicating whether the memory block at the memory currently contains data of the first cacheline or data corresponding to a second cacheline. The first and second cachelines alternately sharing the swap buffer at the memory. When the decoded status value indicates that the memory block at the first memory currently contains the data corresponding to the first cacheline, an instruction is transmitted to the memory controller to directly write the block of data to the memory block at the first memory.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Patent number: 11321171
    Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 3, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
  • Publication number: 20070181583
    Abstract: A double-walled tank for the transport of fluid, the tank includes a rigid fluid impervious substantially cylindrical inner container concentrically nested within a rigid correspondingly substantially cylindrical outer container, the inner and outer containers having end walls sealing the containers. A grapple mount is mounted to an upper side of an outer surface of the outer container at a substantially medial position substantially medially along the outer container. A lower side of the outer container, opposite the upper side, is reinforced. The grapple mount may include a rigid plate mounted atop the upper side of the outer container at the medial position. An anti-surge baffle is mounted across, so as to extend between and into engagement with, an upper side of the inner container adjacent the baffle mount and a lower side of the inner container adjacent the reinforced lower side of the outer container.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 9, 2007
    Inventor: George Zacharias
  • Publication number: 20060196027
    Abstract: An apparatus for removing pins from, and installing pins into, the track links of an endless track on a track machine includes a frame having a parallel, spaced apart pair of rigid base members, at least four rigid elongate members mounted therebetween so as to extend between and brace the base members. The elongate members and base members define a rectangular polyhedron space formed of the rectangular prismatic array of members, both base and elongate. A first pair of elongate members lie in a first plane. A second pair of elongate members lie in a second plane orthogonal to the first plane. The first and second planes are parallel to the link pins. The base members lie in a third plane orthogonal to the first and second planes. An actuator drives the link pin which is to be removed or replaced coaxially with the intersection of the first and second planes.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 7, 2006
    Inventor: George Zacharias
  • Patent number: 6464094
    Abstract: A stand-by water tank for remote access fine suppression is adapted to be transportable to the fire by grappling of the tank about its balance point by a skidder grapple.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: October 15, 2002
    Inventor: George Zacharias
  • Publication number: 20020020704
    Abstract: A stand-by water tank for remote access fine suppression is adapted to be transportable to the fire by grappling of the tank about its balance point by a skidder grapple.
    Type: Application
    Filed: June 20, 2001
    Publication date: February 21, 2002
    Inventor: George Zacharias
  • Patent number: 4310647
    Abstract: Monoesters of fumaric acid and dicyclopentadienyl alcohol halogenated with one or two atoms of a halogen are compounds useful as reactive diluents for polyesters or vinyl ester resins.
    Type: Grant
    Filed: March 28, 1980
    Date of Patent: January 12, 1982
    Assignee: The Dow Chemical Company
    Inventor: George Zacharias
  • Patent number: D1026866
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 14, 2024
    Assignee: OXIWEAR, INC.
    Inventors: George Donald Beckstein, III, Ben Salthouse, Frederick Zacharias Kruger, Jan Boonzaaier du Preez