Patents by Inventor George Zampetti
George Zampetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094407Abstract: Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.Type: ApplicationFiled: November 16, 2023Publication date: March 21, 2024Inventor: George Zampetti
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Patent number: 11841443Abstract: Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.Type: GrantFiled: March 8, 2022Date of Patent: December 12, 2023Assignee: Microchip Technology IncorporatedInventor: George Zampetti
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Publication number: 20220283316Abstract: Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.Type: ApplicationFiled: March 8, 2022Publication date: September 8, 2022Inventor: George Zampetti
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Publication number: 20080049743Abstract: One embodiment of the present invention sets forth a method for autonomously validating the time and frequency data obtained from multiple sources, and generating a suitable estimate of the frequency difference between the client clock and the source. The method includes the steps of protocol data unit validation, offset measurement, minimum offset filtering, and frequency filtering. With these steps, the negative effects of packet delay variation may be mitigated and a frequency estimate is determined for the source in question, together with an associated validity status. Consequently, quality control of the local clock is achieved in packet networks at significantly reduced cost and decreased level of complexity relative to prior art approaches.Type: ApplicationFiled: January 31, 2007Publication date: February 28, 2008Inventor: George Zampetti
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Patent number: 6943609Abstract: A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.Type: GrantFiled: February 19, 2004Date of Patent: September 13, 2005Assignee: Symmetricom IncInventors: George Zampetti, Bob Hamilton
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Patent number: 6876242Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.Type: GrantFiled: February 19, 2004Date of Patent: April 5, 2005Assignee: Symmetricom, Inc.Inventors: George Zampetti, Bob Hamilton
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Publication number: 20040164776Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an.input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.Type: ApplicationFiled: February 19, 2004Publication date: August 26, 2004Inventors: George Zampetti, Bob Hamilton
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Publication number: 20040164782Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.Type: ApplicationFiled: February 19, 2004Publication date: August 26, 2004Inventors: George Zampetti, Bob Hamilton
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Patent number: 6765424Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.Type: GrantFiled: November 20, 2001Date of Patent: July 20, 2004Assignee: Symmetricom, Inc.Inventors: George Zampetti, Bob Hamilton
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Patent number: 5751777Abstract: A dual locked loop is disclosed comparing preferably a GPS signal with an E1 signal and the E1 signal with the output of the loop. The GPS signal is low pass filtered to provide a low pass filtered GPS versus E1 signal that is used as a calibration for a closed loop having a second low pass filter for filtering the comparisons of the E1 and the output signal. By appropriately selecting the filter parameters, the output stability can track the stability of the local oscillator driving the NCO for short term stability, the medium term stability of the E1 signal and the long term stability of the GPS signal.Type: GrantFiled: May 3, 1996Date of Patent: May 12, 1998Assignee: SymmetriCom, Inc.Inventor: George Zampetti