Abstract: The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a second zone doped by a second type of dopant. The channel is doped by the second type of dopant. The gate insulator comprises a first part corresponding to the first doped zone and a second part corresponding to the second doped zone of the gate. The first part of the gate insulator has a higher tunnel resistance than the second part. Data storage is realized by means of charge carrier transportation from the gate to the floating substrate through the lower tunnel resistance part of the gate insulator.

Abstract: The capacitorless DRAM memory cell is constituted by a partially-depleted MOSFET device successively comprising a base substrate, a buried insulator, a floating substrate from semiconducting material including a channel, the gate insulator and a gate. The gate comprises a first zone doped by a first type of dopant and a second zone doped by a second type of dopant. The channel is doped by the second type of dopant. The gate insulator comprises a first part corresponding to the first doped zone and a second part corresponding to the second doped zone of the gate. The first part of the gate insulator has a higher tunnel resistance than the second part. Data storage is realized by means of charge carrier transportation from the gate to the floating substrate through the lower tunnel resistance part of the gate insulator.

Abstract: The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a doped central part (140), located between the source and drain regions, and separated from said source and drain regions.

Abstract: A method of producing a transistor with a highly doped zone situated between lightly doped zones. This method comprises: a first oblique implant of ions (100) into a first and a second zone (144, 142), a mask (114) being formed at the periphery of a third zone in order to protect the third zone from the ions of the first implant, a second oblique implant of ions (130) into the first and third zones, a mask (115) being formed at the periphery of the second zone (142) in order to protect the second zone (142) from the ions (130) of the second implant, then the formation of a gate of the transistor.