Abstract: A computer and method that can be used in digital computers to calculate the inverse I of a number D. The inverse is approximated by I2 after the application of a complementary correction Cjl to an approximation I1 obtained by linear approximation on the basis of a first value Io which in turn is obtained on the basis of an inverse table. The correction value Cjl is obtained from pre-established data CBl and Hj that are memorized in tables of reduced dimensions.

Abstract: The invention is in the realm of an information processing system including a central unit which includes several processors sending requests to several processors sending requests to several memories via an input interconnection and receiving responses from those memories via an output interconnection. To simplify the input interconnection when the number of processors and memories increases, a ring of stations equipped with a register is used. A request given by a processor is loaded into a station when that station is free or becomes free, If not the ring functions a fed back shift register. A station becomes free when the request contained in the station downstream is accepted by a memory. An analogous device can be used for the output interconnection. A notable application is vector processing.

Abstract: A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.

Abstract: A central unit for a data-processing system having a high degree of parallelism. This central unit includes a number of basic processors sending requests to a number of modules in receiving responses from those modules. To simplify the interconnection between the modules and the processors when their number increases, the invention is characterized wherein the requests sent from each processor are transmitted to the input of each of said modules via an input shift register, wherein the response coming from each of the said modules are transmitted to the input of each processor via an output shift register, wherein for any provided processor, the number of stages of said input shift register making it possible to access the modules is different for each of the modules and wherein for any processor, the total number of stages belonging to the input and output shift registers associated with one of the said modules is constant and independent of the module and processor in question.