Abstract: A method for transferring an element of binary information of the differential type present on two first bit lines to two second bit lines through a differential amplifier. The method includes a precharging phase followed by an evaluation phase of the first bit lines. The precharging phase consists of short-circuiting the first bit lines to each other and short-circuiting at least one of the second bit lines to the first bit lines. Such a differential amplifier may be utilized in an electronic circuit and assembly such as a carry select adder circuit.

Abstract: A peak clipping circuit for an integrated circuit of the VLSI type is connected in parallel with the integrated circuit and includes a peak clipping transistor of the bipolar T type and a charge transistor M of the MOS type. The charge transistor has its gate connected to an input of a circuit device of the integrated circuit. The clipping circuit functions to minimize parasitic oscillations at the working level of the input signal.

Abstract: For use with an inverter including CMOS transistors, a device for compensating inherent variations in electrical properties among MOS integrated circuits, the device including a generator of a reference signal representing conduction of a reference transistor; two threshold amplifiers; two switches; and two compensating transistors. If, for example, a first transistor is weak, switches are employed to selectively activate one or more supplementary transistors to add a compensating current to a current furnished by the first transistor so as to provide a reliably uniform output current as compared with a plurality of other MOS integrated circuits.

Abstract: An integrated binary amplifier connected to a bus such as a precharged bus and having a field effect transistor receiving an input signal and coupled to series-connected bipolar transistors including an output transistor. The base of the output transistor is connected to a fixed potential by a field effect transistor of which the type and the control means assure its conduction when the bipolar transistors are conductive. The output signal thus has its low level to ground.

Abstract: Each programming point (11) of the programmable logic network (10) according to the invention is made with a field effect transistor (N1), the gate and drain of which are connected respectively to the input (Lx) and output (Ly) lines, and the source of which is connected both to the reference potential, via the drain-to-source path of a second field effect transistor (N2), the gate of which is connected to the output line (Ly), and to the base of a bipolar transistor Q, the emitter-to-collector path of which is disposed between the ground and output lines. A network according to the invention has an increased operating speed and can be used in a read-only memory or in PLA circuits.