Patents by Inventor Georgia Penido Safe
Georgia Penido Safe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10990734Abstract: Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.Type: GrantFiled: December 16, 2019Date of Patent: April 27, 2021Assignee: Cadence Design Systems, Inc.Inventors: Georgia Penido Safe, Vincent Gregory Reynolds, Adriana Cassia Rossi de Almeida Braz, Julio Alexandre Silva Rezende
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Patent number: 10956640Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.Type: GrantFiled: July 10, 2019Date of Patent: March 23, 2021Assignee: Cadence Design Systems, Inc.Inventors: Georgia Penido Safe, Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga, Lucas Martins Chaves, Pedro Bruno Neri Silva, Mariana Ferreira Marques, Vincent Gregory Reynolds
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Patent number: 10409945Abstract: Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.Type: GrantFiled: June 29, 2015Date of Patent: September 10, 2019Assignee: Cadence Design Systems, Inc.Inventors: Chung-Wah Norris Ip, Georgia Penido Safe, Guilherme Henrique de Sousa Santos, Adriana Cassia Rossi de Almeida Braz
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Patent number: 10380295Abstract: Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.Type: GrantFiled: March 31, 2016Date of Patent: August 13, 2019Assignee: Cadence Design Systems, Inc.Inventors: Chung-Wah Norris Ip, Georgia Penido Safe
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Patent number: 9477802Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: October 25, 2016Assignee: Cadence Design Systems, Inc.Inventors: Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Beth C. Isaksen, Georgia Penido Safe
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Patent number: 8527911Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: September 3, 2013Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
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Patent number: 8458621Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: June 4, 2013Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
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Patent number: 8205187Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: June 19, 2012Assignee: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, Chung-Wah Norris Ip, Harry David Foster, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Georgia Penido Safe