Abstract: A transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The transmitter includes an Integrated Circuit architecture and partition that relaxes the bandwidth and linearity constraints of a gearbox-to-laser driver interface. In the proposed architecture, the gearbox Integrated Circuit aligns two or more digital data streams and transmits the aligned two or more data streams to the laser driver via separate signals.

Abstract: An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.

Abstract: A connector assembly is provided that mates on one side with an optical transceiver module holder and that electrically connects on the opposite side with an external system circuit board. When the connector assembly is mated with an optical transceiver module holder, a base of a parallel optical transceiver module held in the holder mates with a socket of the connector assembly such that respective arrays of electrical contacts disposed on the base and in the socket come into contact with one another. At least one gearbox IC for performing data rate conversion is mounted on the assembly circuit board. A lower surface of the assembly circuit board has an array of electrical contacts on it that are in contact with an array of electrical contacts disposed on the surface of the external system circuit board on which the connector assembly is mounted.

Abstract: An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.

Abstract: A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Abstract: A Tx IC and an Rx IC that use different supply voltages are mounted on a circuit board and interfaced via traces of the board. The configuration of the Tx IC is such that DC decoupling is provided between the ICs while also preventing inadvertent turn-on of the ESD diodes of the Rx IC. These features make it possible to provide DC decoupling between high-performance Tx ICs that use relatively high supply voltages and Rx ICs that use relatively low supply voltages without the need for AC coupling capacitors and while also preventing ESD protection of the Rx IC from being degraded.

Abstract: A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Abstract: A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC performs data rate conversion and phase alignment. In the transmit direction, the gearbox IC receives N lanes of electrical data signals having a data rate of X Gbps and outputs N/2 lanes of electrical data signals having a data rate of 2X Gbps. In the receive direction, the gearbox IC receives N/2 electrical data signals having a data rate of 2X Gbps and converts the N/2 electrical data signals into N electrical data signals having a data rate of X.

Abstract: An optical communication system, a transmitter, a receiver, and methods of operating the same are provided. In particular, a transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The receiver is configured to provide receive and decode to the optical signals received from the transmitter. One or both of the receiver and transmitter are configured to compensate for non-idealities or non-linearities introduced into the communication system by optical components of the system.

Abstract: An optical communication system, a transmitter, a receiver, and methods of operating the same are provided. In particular, a transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The receiver is configured to provide receive and decode to the optical signals received from the transmitter. One or both of the receiver and transmitter are configured to compensate for non-idealities or non-linearities introduced into the communication system by optical components of the system.

Abstract: An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.

Abstract: A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC is compatible with ASIC designs currently used in optical fiber links. The gearbox IC enables the data rate of the optical fiber link to be dramatically increased without requiring a redesign of the ASIC that is currently used in the optical fiber link. The gearbox IC performs data rate conversion and phase alignment for bit streams being transferred via the gearbox IC between the ASIC and an optical transceiver module of the optical communications system.

Abstract: An integrated circuit is incorporated into a communications system to enable a channel to achieve data rates that are at least double that which are currently achievable. The integrated circuit combines serial data signals using recovered clock and serial data signals in reference and non-reference clock domains. The integrated circuit rate converts recovered serial data in one of the clock domains, performs a phase alignment at the converted data rate, and returns the rate converted and phase-aligned serial data to the recovered data rate in response to the recovered clock from the remaining clock domain. Thereafter, the recovered and aligned serial data signals are combined. The phase alignment is monitored in circuitry that detects when a threshold offset is violated. When the threshold offset is violated a synchronization circuit is enabled.

Abstract: A data stream monitor includes an analog front end (AFE) and a digital state machine. The AFE receives recovered clock and data signals at a first rate. The AFE uses the recovered clock and a phase interpolator to generate a phase-adjusted clock signal at a second rate slower than the first rate. The AFE uses a detector operating with the phase-adjusted clock signal to generate a representation of the data signal generated from comparisons of the data signal with two reference voltages. A logical combination of the results from the comparisons generates a signal that identifies when the data signal voltage is near the common-mode voltage. The digital state machine generates a strobe signal at a third rate slower than the second rate. The strobe signal is used by the AFE to sample the signal. The sample is forwarded to the digital state machine where it is stored.

Abstract: An integrated circuit is incorporated into a communications system to enable a channel to achieve data rates that are at least double that which are currently achievable. The integrated circuit combines serial data signals using recovered clock and serial data signals in reference and non-reference clock domains. The integrated circuit rate converts recovered serial data in one of the clock domains, performs a phase alignment at the converted data rate, and returns the rate converted and phase-aligned serial data to the recovered data rate in response to the recovered clock from the remaining clock domain. Thereafter, the recovered and aligned serial data signals are combined. The phase alignment is monitored in circuitry that detects when a threshold offset is violated. When the threshold offset is violated a synchronization circuit is enabled.

Abstract: A data stream monitor includes an analog front end (AFE) and a digital state machine. The AFE receives recovered clock and data signals at a first rate. The AFE uses the recovered clock and a phase interpolator to generate a phase-adjusted clock signal at a second rate slower than the first rate. The AFE uses a detector operating with the phase-adjusted clock signal to generate a representation of the data signal generated from comparisons of the data signal with two reference voltages. A logical combination of the results from the comparisons generates a signal that identifies when the data signal voltage is near the common-mode voltage. The digital state machine generates a strobe signal at a third rate slower than the second rate. The strobe signal is used by the AFE to sample the signal. The sample is forwarded to the digital state machine where it is stored.

Abstract: A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC performs data rate conversion and phase alignment. In the transmit direction, the gearbox IC receives N lanes of electrical data signals having a data rate of X Gbps and outputs N/2 lanes of electrical data signals having a data rate of 2X Gbps. In the receive direction, the gearbox IC receives N/2 electrical data signals having a data rate of 2X Gbps and converts the N/2 electrical data signals into N electrical data signals having a data rate of X.

Abstract: A connector assembly is provided that mates on one side with an optical transceiver module holder and that electrically connects on the opposite side with an external system circuit board. When the connector assembly is mated with an optical transceiver module holder, a base of a parallel optical transceiver module held in the holder mates with a socket of the connector assembly such that respective arrays of electrical contacts disposed on the base and in the socket come into contact with one another. At least one gearbox IC for performing data rate conversion is mounted on the assembly circuit board. A lower surface of the assembly circuit board has an array of electrical contacts on it that are in contact with an array of electrical contacts disposed on the surface of the external system circuit board on which the connector assembly is mounted.

Abstract: An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.

Abstract: A skew adjustor that can reduce inter-pair skew between differential signals received via a cable is disclosed. In one embodiment, a skew adjustor includes: a skew detector that receives signals from a cable, and provides a detected skew amount when skew is detected between two of the signals; an offset controller for receiving the detected skew amount, and for providing a delay control signal in response thereto; and a skew delay circuit that receives the signals and the delay control signal, and enables one or more delay stages in a path of a first arriving of the two skewed signals based on the delay control signal, such that an adjusted skew between the two skewed signals at an output of the skew delay circuit is less than the detected skew amount by an amount corresponding to the enabled one or more delay stages.