Abstract: A device for processing homomorphically encrypted data, preferably including a memory, a number-theoretic transform processing element, and/or a multiply-accumulate processing element. The memory can preferably be accessed by row or column through XOR-based address mapping procedures performed at a permutation processing element that preferably converts data between conflict-free memory bank ordering and natural ordering, such as wherein the device can receive input data to be stored in the memory and/or send output data from the memory to a processing board. The multiply-accumulate processing element can preferably perform a key-switching operation using a key-switching key and the input data, wherein a first half of the key-switching key is randomly generated at a random number generator. The multiply-accumulate processing element can include a command input with pipeline stages, a register file, a plurality of multiplexers, a multiplier, and/or an adder.

Abstract: A method for reducing calculation time for processing fully homomorphic encrypted (FHE) data comprises pre-calculating a second half of a key-switching key, storing the second half of the key-switching key in memory, and receiving FHE data. After the FHE data is received, the method determines a first half of the key-switching key by randomly generating a first half of the key-switching key. The key-switching key is then constructed by retrieving the second half of the key-switching key from the memory and appending the second half of the key-switching key to the first half of the key-switching key. After the key has been constructed, a key-switching operation is performed on the FHE data using the key-switching key.

Abstract: A device for processing homomorphically encrypted data, preferably including a memory, a number-theoretic transform processing element, and/or a multiply-accumulate processing element. The memory can preferably be accessed by row or column through XOR-based address mapping procedures performed at a permutation processing element that preferably converts data between conflict-free memory bank ordering and natural ordering, such as wherein the device can receive input data to be stored in the memory and/or send output data from the memory to a processing board. The multiply-accumulate processing element can preferably perform a key-switching operation using a key-switching key and the input data, wherein a first half of the key-switching key is randomly generated at a random number generator. The multiply-accumulate processing element can include a command input with pipeline stages, a register file, a plurality of multiplexers, a multiplier, and/or an adder.

Abstract: A device for processing fully homogeneous encrypted data comprises a command input with pipeline stages and a register file coupled to the command input via a non-pipelined stage and an ultimate pipelined stage. Further, the device includes various multiplexers to allow for usage of a multiplier for different command functions. Moreover, the device includes an adder element with a first input coupled to multiplexer outputs, a select line coupled to a penultimate pipeline stage of the command input, and an output coupled to the register file. A command on the command line passes through the pipeline stages as select inputs to the multiplexers to control the function of the multiplexers at that time.

Abstract: A device for executing programs and processing data that have been homomorphically encrypted is presented. The device includes an interface to a host system board, a mass memory, and a high-speed bus interconnect coupled to the mass memory and the interface. Further, a dedicated fully homomorphic encryption accelerator is coupled to the mass memory, the high-speed bus interconnect, and the interface. The interface both receives input data to be stored in the mass memory and sends output data from the mass memory to the processing board. The dedicated fully homomorphic encryption accelerator converts the input data to output data by performing operations on the input data.

Abstract: A method for conflict-free memory accesses comprises storing data in a memory. The memory can be accessed by row or column, and the data is arranged in a scrambled ordering. Further, the process includes defining a bank as a specified row exclusive or-ed with a specific column. When addressing a row, mapping a bank i to an index i xor the row. On the other hand, when addressing a column, mapping a bank i to an index i xor the row.

Abstract: A method for reducing calculation time for processing fully homomorphic encrypted (FHE) data comprises pre-calculating a second half of a key-switching key, storing the second half of the key-switching key in memory, and receiving FHE data. After the FHE data is received, the method determines a first half of the key-switching key by randomly generating a first half of the key-switching key. The key-switching key is then constructed by retrieving the second half of the key-switching key from the memory and appending the second half of the key-switching key to the first half of the key-switching key. After the key has been constructed, a key-switching operation is performed on the FHE data using the key-switching key.

Abstract: A device for processing fully homogeneous encrypted data comprises a command input with pipeline stages and a register file coupled to the command input via a non-pipelined stage and an ultimate pipelined stage. Further, the device includes various multiplexers to allow for usage of a multiplier for different command functions. Moreover, the device includes an adder element with a first input coupled to multiplexer outputs, a select line coupled to a penultimate pipeline stage of the command input, and an output coupled to the register file. A command on the command line passes through the pipeline stages as select inputs to the multiplexers to control the function of the multiplexers at that time.

Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.

Abstract: Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.

Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.

Abstract: Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.

Abstract: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.

Abstract: The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.