Abstract: A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle.