Patents by Inventor Georgios Petkos
Georgios Petkos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7122433Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).Type: GrantFiled: April 9, 2004Date of Patent: October 17, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven T. Peake, Georgios Petkos, Philip Rutter, Raymond J. Grover
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Patent number: 6800900Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).Type: GrantFiled: August 6, 2002Date of Patent: October 5, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven T. Peake, Georgios Petkos, Philip Rutter, Raymond J. Grover
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Publication number: 20040188775Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).Type: ApplicationFiled: April 9, 2004Publication date: September 30, 2004Inventors: Steven T. Peake, Georgios Petkos, Philip Rutter, Raymond J. Grover
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Patent number: 6660591Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window (18a) for a source electrode (33) can be self-aligned to a narrow trench (20) containing the trench-gate (11). Thereby, the channel-accommodating region (15) can also be provided after forming the trench-gate (11), and with very good control of its doping concentration (Na; p) adjacent to the trench (20). To achieve this control, its dopant is provided after removing the spacers (52) from the mask (51) so as to form a doping window (51b), which may also be used for the source dopant, adjacent to the trench-gate (11). A high energy dopant implant (61) or other doping process provides this channel dopant adjacent to the trench (20) and extending laterally below the mask (51,51n).Type: GrantFiled: April 26, 2002Date of Patent: December 9, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven T. Peake, Georgios Petkos, Robert J. Farr, Christopher M. Rogers, Raymond J. Grover, Peter J. Forbes
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Patent number: 6534367Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).Type: GrantFiled: April 26, 2002Date of Patent: March 18, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven T. Peake, Georgios Petkos, Robert J. Farr, Christopher M. Rogers, Raymond J. Grover, Peter J. Forbes
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Publication number: 20030047779Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).Type: ApplicationFiled: August 6, 2002Publication date: March 13, 2003Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Steven T. Peake, Georgios Petkos, Philip Rutter, Raymond J. Grover
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Publication number: 20020160573Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).Type: ApplicationFiled: April 26, 2002Publication date: October 31, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Steven T. Peake, Georgios Petkos, Robert J. Farr, Christopher M. Rogers, Raymond J. Grover, Peter J. Forbes
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Publication number: 20020160557Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window (18a) for a source electrode (33) can be self-aligned to a narrow trench (20) containing the trench-gate (11). Thereby, the channel-accommodating region (15) can also be provided after forming the trench-gate (11), and with very good control of its doping concentration (Na; p) adjacent to the trench (20). To achieve this control, its dopant is provided after removing the spacers (52) from the mask (51) so as to form a doping window (51b), which may also be used for the source dopant, adjacent to the trench-gate (11). A high energy dopant implant (61) or other doping process provides this channel dopant adjacent to the trench (20) and extending laterally below the mask (51, 51n).Type: ApplicationFiled: April 26, 2002Publication date: October 31, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Steven T. Peake, Georgios Petkos, Robert J. Farr, Christopher M. Rogers, Raymond J. Grover, Peter J. Forbes