Abstract: A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.

Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.

Abstract: A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Abstract: A system for facilitating assembly language programming by providing a sophisticated hybrid programming environment comprising a module to parse input hybrid source code files containing at least one high-level instruction; a library of functions for defining at least one assembly-language instruction in the hybrid source code file from a corresponding high-level instruction; a module for translating the high-level instructions into machine language instructions according to the library; and a module to output the translated machine language instructions into an object file.

Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.