Patents by Inventor Georgy Viktorovich Vitaliev

Georgy Viktorovich Vitaliev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4077029
    Abstract: An associative memory includes storage units each of which includes an address storage module and an interrogation decoder connected thereto by address buses; an interrogation register having flip-flops connected to the inputs of respective interrogation decoders; detectors connected to the storage units by digit buses; a complementary interrogation decoder to drive respective detectors; a complementary interrogation register to receive and store the complementary interrogation code represented by a complementary given set of binary descriptors, the register comprising a given number of flip-flops connected to respective inputs of the complementary interrogation decoder and to the complementary inputs of the interrogation decoders of the storage units, while the outputs of the complementary interrogation decoder are connected to the complementary inputs of the respective detectors.
    Type: Grant
    Filed: February 11, 1976
    Date of Patent: February 28, 1978
    Inventors: Georgy Viktorovich Vitaliev, Alexei Davidovich Gvinepadze, Rem Vasilievich Smirnov, Gury Dmitrievich Sofiisky
  • Patent number: 4069473
    Abstract: This application discloses an associative memory designed to perform search and logical operations on attributive information presented in the form of multi-digit associative words or in the form of sets consisting of a given number of binary associative indications. The associative memory comprises an input register, an interrogation register, groups of coincidence circuits, groups of OR circuits, a mask register, an operation decoder and a data storage unit. The input register, the interrogation register and the mask register are made up of flip-flops. The number of flip-flops in the interrogation register and in the mask register, the number of said coincidence circuits and the number of said OR circuits are equal to the number of flip-flops of said input register, which is equal to the number of binary indications in said code of the first operand. Two coincidence circuits are in each group of such circuits, and two OR circuits are in each group of these circuits.
    Type: Grant
    Filed: October 14, 1976
    Date of Patent: January 17, 1978
    Inventors: Georgy Viktorovich Vitaliev, Alexei Davidovich Gvinepadze, Rem Vasilievich Smirnov, Gury Dmitrievich Sofiisky