Patents by Inventor Geraint M. North
Geraint M. North has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163702Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: December 16, 2019Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Simon Murray, Geraint M. North
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Patent number: 11119949Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: December 16, 2019Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Simon Murray, Geraint M. North
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Patent number: 11061833Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: December 16, 2019Date of Patent: July 13, 2021Assignee: International Business Machines CorporationInventors: Simon Murray, Geraint M. North
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Publication number: 20200133888Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: December 16, 2019Publication date: April 30, 2020Inventors: Simon Murray, Geraint M. North
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Publication number: 20200133889Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: December 16, 2019Publication date: April 30, 2020Inventors: Simon Murray, Geraint M. North
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Publication number: 20200117615Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Simon Murray, Geraint M. North
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Patent number: 10534727Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: October 11, 2016Date of Patent: January 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Murray, Geraint M. North
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Publication number: 20170031839Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: October 11, 2016Publication date: February 2, 2017Inventors: Simon Murray, Geraint M. North
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Patent number: 9483419Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: April 25, 2014Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Murray, Geraint M. North
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Publication number: 20140237199Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Murray, Geraint M. North
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Patent number: 8719541Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: GrantFiled: November 11, 2008Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Simon Murray, Geraint M. North
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Patent number: 8108842Abstract: A native binding technique is provided for inserting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.Type: GrantFiled: October 1, 2008Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Alexander B. Brown, Geraint M. North, Frank Thomas Weigel, Gareth Anthony Knight
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Patent number: 8091076Abstract: A native binding technique is provided for insetting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.Type: GrantFiled: September 25, 2008Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: Alexander B. Brown, Geraint M. North, Frank Thomas Weigel, Gareth Anthony Knight
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Patent number: 8024555Abstract: An emulator allows subject code written for a subject processor having subject processor registers and condition code flags to run in a non-compatible computing environment. The emulator identifies and records parameters of instructions in the subject code that affect status of the subject condition code flags. Then, when an instruction in the subject code is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.Type: GrantFiled: December 14, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: John H. Sandham, Geraint M. North
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Patent number: 7895407Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.Type: GrantFiled: November 19, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Gisle Dankel, Geraint M. North, Miles Philip Howson, Gavin Barraclough
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Publication number: 20100030975Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: November 11, 2008Publication date: February 4, 2010Applicant: Transitive LimitedInventors: Simon Murray, Geraint M. North
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Publication number: 20090100416Abstract: A native binding technique is provided for insetting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.Type: ApplicationFiled: September 25, 2008Publication date: April 16, 2009Applicant: TRANSITIVE LIMITEDInventors: Alexander B. BROWN, Geraint M. NORTH, Frank Thomas WEIGEL, Gareth Anthony KNIGHT
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Publication number: 20080140971Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.Type: ApplicationFiled: November 19, 2007Publication date: June 12, 2008Applicant: Transitive LimitedInventors: Gisle Dankel, Geraint M. North, Miles P. Howson, Gavin Barraclough
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Publication number: 20030149963Abstract: An emulator (30) allows subject code (10) written for a subject processor (12) having subject processor registers (14) and condition code flags (16) to run in a non-compatible computing environment (2). The emulator (3) identifies and records parameters of instructions in the subject code (10) that affect status of the subject condition code flags (16). Then, when an instruction in the subject code (10) is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.Type: ApplicationFiled: December 5, 2002Publication date: August 7, 2003Inventors: John Sandham, Geraint M. North