Patents by Inventor Geraint M. North

Geraint M. North has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163702
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 11119949
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 11061833
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20200133888
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 30, 2020
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20200133889
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 30, 2020
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20200117615
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 10534727
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20170031839
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 9483419
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20140237199
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 8719541
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Simon Murray, Geraint M. North
  • Patent number: 8108842
    Abstract: A native binding technique is provided for inserting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alexander B. Brown, Geraint M. North, Frank Thomas Weigel, Gareth Anthony Knight
  • Patent number: 8091076
    Abstract: A native binding technique is provided for insetting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alexander B. Brown, Geraint M. North, Frank Thomas Weigel, Gareth Anthony Knight
  • Patent number: 8024555
    Abstract: An emulator allows subject code written for a subject processor having subject processor registers and condition code flags to run in a non-compatible computing environment. The emulator identifies and records parameters of instructions in the subject code that affect status of the subject condition code flags. Then, when an instruction in the subject code is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: John H. Sandham, Geraint M. North
  • Patent number: 7895407
    Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gisle Dankel, Geraint M. North, Miles Philip Howson, Gavin Barraclough
  • Publication number: 20100030975
    Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
    Type: Application
    Filed: November 11, 2008
    Publication date: February 4, 2010
    Applicant: Transitive Limited
    Inventors: Simon Murray, Geraint M. North
  • Publication number: 20090100416
    Abstract: A native binding technique is provided for insetting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes.
    Type: Application
    Filed: September 25, 2008
    Publication date: April 16, 2009
    Applicant: TRANSITIVE LIMITED
    Inventors: Alexander B. BROWN, Geraint M. NORTH, Frank Thomas WEIGEL, Gareth Anthony KNIGHT
  • Publication number: 20080140971
    Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.
    Type: Application
    Filed: November 19, 2007
    Publication date: June 12, 2008
    Applicant: Transitive Limited
    Inventors: Gisle Dankel, Geraint M. North, Miles P. Howson, Gavin Barraclough
  • Publication number: 20030149963
    Abstract: An emulator (30) allows subject code (10) written for a subject processor (12) having subject processor registers (14) and condition code flags (16) to run in a non-compatible computing environment (2). The emulator (3) identifies and records parameters of instructions in the subject code (10) that affect status of the subject condition code flags (16). Then, when an instruction in the subject code (10) is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.
    Type: Application
    Filed: December 5, 2002
    Publication date: August 7, 2003
    Inventors: John Sandham, Geraint M. North