Abstract: An active filter, capable of being electronically controlled over a 50:1 or greater frequency range, while maintaining a fixed filter characteristic and a constant, nearzero DC offset voltage. The filter utilizes passive element-multipliers, either capacitor-multiplier or resistor-multiplier circuits, as the frequency determining networks, depending upon whether the filter is a low-pass or a high-pass filter. Tuning is accomplished by varying the gain of a variable gain amplifier connected in series with the capacitive or resistive element of the multiplier networks. Also disclosed is an implementation of the variable gain amplifier which permits the filter's cut-off frequency to be controlled digitally. The filter may be designed to have any desired type of filter characteristic. Several filter sections may be connected in cascade to provide any desired number of filter poles.

Abstract: A rate multiplier with which a given input binary pulse train generates an utput pulse train having a rate which is defined by the expressionR.sub.o = (R.sub.in .sup.. x )/(2.sup.. n)where R.sub.o is the output pulse rate, R.sub.in is the input pulse rate, n is the number of stages in a Johnson counter and x is any integer from 0 to 2n-1. The rate multiplier may be built in any of the common solid state technologies and, for any given technology, will operate reliably at a substantially faster rate than is usually possible. A plurality of rate multipliers may be cascaded to provide further control of the output pulse rate. Because of the cascading technique disclosed, only the first rate multiplier need be operable at the maximum required clock rate, with each succeeding cascaded rate multiplier being required to operate at a rate which is only 1/(2 .sup.. n) as fast as the previous rate multiplier.