Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches. Each of two latches receives one set and one reset signal. The third latch receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch and of one of the first two latches. A data signal is applied to the set terminal of the third latch. The other of the first two latches constitutes the output latch and is connected to receive the outputs of the remaining latches. The output latch produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

Abstract: A latching circuit with reduced signal delay is disclosed comprising a latch and an output logic function circuit. The same signals are applied to the output gate of the latch and to the logic function circuit, whereby the output gate and the logic function circuit effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal is applied only to the logic function circuit but not to the latch. Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.

Abstract: A hazard-free latch is disclosed comprising three NAND logic gates, one of the gates, in combination with its output loading, being relatively fast and another of the gates, in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate. The output of the fast gate is connected to another input of the slow gate. The outputs of the third and the slow gates are connected to an output terminal and to another input of the fast gate.

Abstract: The generation of internal circuit noise due to the switching of differing numbers of bilevel data lines is suppressed by maintaining the energizing current substantially constant with widely varying amounts of current drawn by varying the current drawn by redundant driver circuits, which also generate parity or check signals, to compensate for the difference in current drawn by the designated data driver circuits. The number of redundant driver circuits is reduced by loading the second and further redundant driver circuits for drawing currewnts related to the current drawn by the first redundant driver circuit by succeeding powers of two. Further suppression in internal circuit noise obtains with gating of all driver circuits at the time switching occurs. Control circuitry comprising conventional full adder circuits arranged for expressing the number of data signal lines in a given level is advantageous for controlling the redundant driver circuits and for generating check bits at the same time.