Patents by Inventor Gerald A. Schwoerer
Gerald A. Schwoerer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8464007Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.Type: GrantFiled: June 12, 2009Date of Patent: June 11, 2013Assignee: Cray Inc.Inventors: Dennis C. Abts, Michael Higgins, Van L. Snyder, Gerald A Schwoerer
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Patent number: 8126674Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: August 27, 2010Date of Patent: February 28, 2012Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
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Patent number: 8065573Abstract: Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.Type: GrantFiled: November 19, 2008Date of Patent: November 22, 2011Assignee: Cray Inc.Inventors: Dennis C. Abts, Gerald A Schwoerer, Van L. Snyder
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Publication number: 20100324854Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: August 27, 2010Publication date: December 23, 2010Applicant: CRAY INC.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
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Publication number: 20100318741Abstract: A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L1 data cache is local to each of the plurality of processors, and an L2 cache is local to each of the plurality of processors. An L3 cache is local the node but shared among the plurality of processors, and the L3 cache is a subset of data stored in the local memory. The L2 caches are subsets of the L3 cache, and the L1 caches are a subset of the L2 caches in the respective processors.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: Cray Inc.Inventors: Steven L. Scott, Gregory J. Faanes, Abdulla Bataineh, Michael Bye, Gerald A. Schwoerer, Dennis C. Abts
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Patent number: 7826996Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: February 26, 2007Date of Patent: November 2, 2010Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
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Patent number: 7676728Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: GrantFiled: November 10, 2006Date of Patent: March 9, 2010Assignee: Cray Inc.Inventors: David R. Resnick, Van L. Snyder, Michael F. Higgins, Alan M. Grossmeier, Kelly J. Marquardt, Gerald A. Schwoerer
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Publication number: 20090287889Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.Type: ApplicationFiled: June 12, 2009Publication date: November 19, 2009Inventors: Dennis C. Abts, Michael Higgins, Van L. Snyder, Gerald A. Schwoerer
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Publication number: 20090177932Abstract: Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.Type: ApplicationFiled: November 19, 2008Publication date: July 9, 2009Inventors: Dennis C. Abts, Gerald A. Schwoerer, Van L. Snyder
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Publication number: 20080059105Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: February 26, 2007Publication date: March 6, 2008Applicant: CRAY INC.Inventors: David Resnick, Gerald Schwoerer, Kelly Marquardt, Alan Grossmeier, Michael Steinberger, Van Snyder, Roger Bethard
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Patent number: 7320100Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: GrantFiled: May 19, 2004Date of Patent: January 15, 2008Assignee: Cray Inc.Inventors: R. Paul Dixon, David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard, Michael F. Higgins
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Publication number: 20070113150Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: ApplicationFiled: November 10, 2006Publication date: May 17, 2007Applicant: CRAY INC.Inventors: David Resnick, Van Snyder, Michael Higgins, Alan Grossmeier, Kelly Marquardt, Gerald Schwoerer
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Patent number: 7184916Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: GrantFiled: May 19, 2004Date of Patent: February 27, 2007Assignee: Cray Inc.Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
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Publication number: 20050022065Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.Type: ApplicationFiled: May 19, 2004Publication date: January 27, 2005Inventors: R. Dixon, David Resnick, Gerald Schwoerer, Kelly Marquardt, Alan Grossmeier, Michael Steinberger, Van Snyder, Roger Bethard, Michael Higgins
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Publication number: 20040267481Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.Type: ApplicationFiled: May 19, 2004Publication date: December 30, 2004Inventors: David R. Resnick, Gerald A. Schwoerer, Kelly J. Marquardt, Alan M. Grossmeier, Michael L. Steinberger, Van L. Snyder, Roger A. Bethard
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Patent number: 6233704Abstract: A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.Type: GrantFiled: March 13, 1996Date of Patent: May 15, 2001Assignee: Silicon Graphics, Inc.Inventors: Steven L. Scott, Steven M. Oberlin, Daniel L. Kunkel, Gerald A. Schwoerer
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Patent number: 5958017Abstract: A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undelivered requests and unanswered requests. The mechanism regulates congestion on the network by throttling back or ratcheting up the allowed number of undelivered requests and unanswered requests based upon the level of busy and non-busy results of such requests and answers. Congestion is also alleviated by the implementation of a set of large and small send and receive buffers. These buffers are configurably partitioned among virtual I/O channels. Each request virtual I/O channel may utilitize congestion control.Type: GrantFiled: September 23, 1997Date of Patent: September 28, 1999Assignee: Cray Research, Inc.Inventors: Steven L. Scott, Richard D. Pribnow, Peter G. Logghe, Daniel L. Kunkel, Gerald A. Schwoerer
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Patent number: 5748900Abstract: A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undelivered requests and unanswered requests. The mechanism regulates congestion on the network by throttling back or ratcheting up the allowed number of undelivered requests and unanswered requests based upon the level of busy and non-busy results of such requests and answers. Congestion is also alleviated by the implementation of a set of large and small send and receive buffers. These buffers are configurably partitioned among virtual I/O channels. Each request virtual I/O channel may utilitize congestion control.Type: GrantFiled: March 13, 1996Date of Patent: May 5, 1998Assignee: Cray Research, Inc.Inventors: Steven L. Scott, Richard D. Pribnow, Peter G. Logghe, Daniel L. Kunkel, Gerald A. Schwoerer
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Patent number: H1176Abstract: Improved error detection and correction is obtained in computers of the type possessing multi-bit memory devices. The error detection involves dispersing the bits from each multi-bit memory device in such a way that a SEC-DED codeword can detect when the multi-bit memory device fails.Type: GrantFiled: August 30, 1989Date of Patent: April 6, 1993Assignee: Cray Research, Inc.Inventor: Gerald A. Schwoerer