Patents by Inventor Gerald Aberdeen Miller

Gerald Aberdeen Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS digital circuits with resistive shunt feedback amplifier
    Patent number: 3986041
    Abstract: A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.
    Type: Grant
    Filed: December 20, 1974
    Date of Patent: October 12, 1976
    Assignee: International Business Machines Corporation
    Inventors: Frederick Buckley, III, Malcom Kenneth Creamer, Jr., Gerald Aberdeen Miller
  • CMOS digital circuits with active shunt feedback amplifier
    Patent number: 3986043
    Abstract: A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.
    Type: Grant
    Filed: December 20, 1974
    Date of Patent: October 12, 1976
    Assignee: International Business Machines Corporation
    Inventors: Frederick Buckley, III, Gerald Aberdeen Miller, Vincent Anthony Scotto