Abstract: A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.

Abstract: An analog to digital converter is fabricated using CMOS construction and uses a successive approximation register to develop the bits in a digital word. A digital to analog converter converts the digital word to analog voltages which are compared with the analog input. The comparator is coupled to the register so as to determine its word bit sequence. The digital words most significant bit is set first in accordance with whether the analog input is greater or less than half of the reference voltage. Then the next most significant bit is evaluated and this process is continued until the least significant bit is evaluated at which time the conversion is complete. In the CMOS circuit, a switched comparator is employed and it draws a capacitor charging current in its operation. Accordingly, it is useful to buffer the comparator input. Two buffers are employed, one p-type and one n-type. They have common inputs and outputs that are selected as a function of the most significant bit in the digital word.

Abstract: Buffer means are included in the input circuit in a switching comparator. The unavoidable shunt capacitance at the comparison node is thereby isolated from the input terminal. This substantially reduces the comparator d-c input loading to improve comparison accuracy particularly with sources having appreciable internal resistance.