Abstract: An all events trace gatherer for a logic simulation machine is disclosed. The all events trace gatherer generates an all events trace (AET) which is a record of what has happened to all or a subset of the facilities by monitoring a simulation bus on which the logic simulation machine put a calculated result during the simulation thereon. The AET gatherer allows an AET to be gathered without slowing the simulation. The AET gatherer is an auxiliary processor that is connected to the simulation bus in the logic simulation machine in parallel with simulation processors of the machine.

Abstract: A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.