Patents by Inventor Gerald Briat

Gerald Briat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11650738
    Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: May 16, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Gerald Briat, Stephane Marmey
  • Publication number: 20230129599
    Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 27, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Gerald BRIAT
  • Patent number: 11567558
    Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 31, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Gerald Briat
  • Patent number: 11392453
    Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 19, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Gerald Briat, Antoine De-Muynck, Alessandro Bastoni, Stephane Marmey
  • Patent number: 11106582
    Abstract: A device includes first and second buffers fillable with contents of memory locations. A selection circuit is configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers. In some examples, the device can be a system on a chip that includes a non-volatile memory and a processor.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 31, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: Gerald Briat
  • Publication number: 20210173469
    Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Gerald BRIAT
  • Publication number: 20210173568
    Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Gerald BRIAT, Stephane MARMEY
  • Publication number: 20210011727
    Abstract: In an embodiment a method for operating an integrated circuit includes sequentially requesting, by a processor of an integrated circuit, different instruction lines; determining, by a first comparator of the integrated circuit, while the processor processes a current instruction line supplied in response to a corresponding request, whether or not at least one of the instructions of the current instruction line is a branch instruction by comparing the at least one of the instructions to reference instructions; executing, by the processor, all instructions of the current instruction line before executing a next instruction line when the at least one instruction is a branch instruction from a program memory of the integrated circuit; and executing, by the processor, all instruction of the current instruction line before executing a next instruction line from first and second volatile memory of the integrated circuit when the at least one instruction is not a branch instruction.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Inventors: Michael Giovannini, Gerald Briat
  • Publication number: 20200081776
    Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Gerald BRIAT, Antoine DE-MUYNCK, Alessandro BASTONI, Stephane MARMEY
  • Publication number: 20200057719
    Abstract: A device includes first and second buffers fillable with contents of memory locations. A selection circuit is configured to select a filling mode between simultaneous filling of the buffers and sequential filling of the buffers. In some examples, the device can be a system on a chip that includes a non-volatile memory and a processor.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 20, 2020
    Inventor: Gerald Briat