Abstract: A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active.

Abstract: A method includes estimating a temperature change to an integrated circuit, which is associated with a pending transmission from the integrated circuit. The method includes, based on the estimated temperature change, regulating at least one parameter that is associated with the pending transmission to maintain a temperature of the integrated circuit below a temperature threshold.

Abstract: A method includes estimating a temperature change to an integrated circuit, which is associated with a pending transmission from the integrated circuit.

Abstract: A circuit includes a temperature sensor configured to determine a circuit temperature and includes an analog circuit including one or more controllable circuit elements. The analog circuit includes at least one adjustable parameter. The circuit further includes a controller coupled to the temperature sensor and configured to select a threshold temperature. The controller is configured to control the analog circuit in response to the circuit temperature to selectively adjust at least one adjustable parameter of the analog circuit when the temperature exceeds the selected threshold temperature.

Abstract: A circuit includes a temperature sensor configured to determine a circuit temperature and includes an analog circuit including one or more controllable circuit elements. The analog circuit includes at least one adjustable parameter. The circuit further includes a controller coupled to the temperature sensor and configured to select a threshold temperature. The controller is configured to control the analog circuit in response to the circuit temperature to selectively adjust at least one adjustable parameter of the analog circuit when the temperature exceeds the selected threshold temperature.

Abstract: A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

Abstract: A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A frequency modulation (FM) radio receiver includes a processing unit that may generate a magnitude value corresponding to a signal strength of each of a plurality of digital samples of a received FM signal. The receiver also includes a noise estimation unit that may filter the magnitude values using a high pass filter and may generate a noise value representative of a noise portion of the received FM signal based upon the filtered magnitude values.