Patents by Inventor Gerald D. Robinson

Gerald D. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12201825
    Abstract: An implantable medical device assembly comprises a sealed housing; a motor including a rotating output shaft within the sealed housing; a first coaxial shaft within the sealed housing, the first coaxial shaft being mechanically coupled to the rotating output shaft such that rotation of the rotating output shaft drives rotation of the first coaxial shaft; a second coaxial shaft external to the sealed housing, the second coaxial shaft being in axial alignment with the first coaxial shaft; an oscillating component mechanically coupling the first coaxial shaft to the second coaxial shaft, wherein rotation of the rotating first coaxial shaft drives the oscillation of the oscillating component, wherein the oscillation of the oscillating component drives rotation of the second coaxial shaft; and a flexible seal including the oscillating component. The sealed housing and the flexible seal combine to form a substantially sealed enclosure encasing the motor and the first coaxial shaft.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 21, 2025
    Assignee: Medtronic, Inc.
    Inventors: Reginald D. Robinson, Mary E. Robischon, Rodney J. Haberle, Gerald G. Lindner, Don A. Rutledge, Jason R. Simoneau
  • Patent number: 6078070
    Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: June 20, 2000
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Gerald D. Robinson
  • Patent number: 5811322
    Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: September 22, 1998
    Assignee: W. L. Gore & Associates, Inc.
    Inventor: Gerald D. Robinson
  • Patent number: 5804847
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: September 8, 1998
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Gerald D. Robinson
  • Patent number: 5663075
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: September 2, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Gerald D. Robinson
  • Patent number: 5242711
    Abstract: A high temperature resist process is combined with microlithographic patterning for the production of materials, such as diamond films, that require a high temperature deposition environment. A conventional polymeric resist process may be used to deposit a pattern of high temperature resist material. With the high temperature resist in place and the polymeric resist removed, a high temperature deposition process may proceed without degradation of the resist pattern. After a desired film of material has been deposited, the high temperature resist is removed to leave the film in the pattern defined by the resist. For diamond films, a high temperature silicon nitride resist can be used for microlithographic patterning of a silicon substrate to provide a uniform distribution of diamond nucleation sites and to improve diamond film adhesion to the substrate.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: September 7, 1993
    Assignee: Rockwell International Corp.
    Inventors: Jeffrey D. DeNatale, John F. Flintoff, Alan B. Harker, Patrick J. Hood, Gerald D. Robinson
  • Patent number: 5219713
    Abstract: The method of constructing an air bridge on a substrate between spaced apart conductors on the substrate with the bridge spanning the distance between the conductors, by using PMGI to build a bridge pad on the substrate; using PMMA to build a bridge pattern over the pad with the ends of said conductors extending into said pattern; depositing titanium and gold over said pad within said pattern by directing the titanium and gold into said pattern onto said pad and conductor ends using relative motion between the substrate and the titanium and gold; and removing the PMGI and PMMA.
    Type: Grant
    Filed: December 17, 1990
    Date of Patent: June 15, 1993
    Assignee: Rockwell International Corporation
    Inventor: Gerald D. Robinson
  • Patent number: 5147740
    Abstract: A mask and lithographic process is disclosed for the formation of conductive patterns on substrates, particularly in connection with the formation of high electron mobility transistors (HEMT) and metal-semiconductor field effect transistors (MESFET). The technique allows the formation of sub-half micron conductive patterns on semiconductor substrates using optical lithography and a multilayer portable conformable mask. The method includes the application of optical contact lithography to a conventional photoresist followed by a deep UV flood exposure of an underlying multilayer PMGI portion. Metal is deposited on a semiconductor substrate through the mask formed by the photoresist and PMGI layers to produce sub-half micron conductive patterns.
    Type: Grant
    Filed: August 9, 1990
    Date of Patent: September 15, 1992
    Assignee: Rockwell International Corporation
    Inventor: Gerald D. Robinson