Abstract: A noise tolerant time division multiplex system including a transmitter and receiver, each constructed as a monolithic integrated circuit and interconnected by a serial data wire. Data as well as power is supplied to the transmitter from a plurality of parallel connected input switches. The transmitter includes a parallel in/serial out shift register controlled by timing logic and further includes a tri-state driver for generating a three-level serial output signal indicative of the status of the input switches. The data is generated at a high rate to eliminate any deleterious effects of noise on the system. The receiver chip receives a regulated energizing potential from the transmitter chip over two additional wires, generates a timing signal from the three-level signal and loads the data in binary format into a serial in/parallel out shift register.