Abstract: In certain embodiments, an air-pressurizing device is positioned to discharge a computer system. A supply conduit pneumatically couples a cooled-air discharge conditioning system with an inlet of the air-pressurizing device.

Abstract: The present invention relates to construction of nonsymmetrical N bit parallel data processing circuits using a plurality of identical integrated circuits chips. In such nonsymmetrical structures it is often impossible to provide a design employing identical integrated circuit chips using conventional techniques. The structure is first divided into single bit slices. These single bit slices are then examined to determine the number of each differing single bit type. A common divisor M is sought for the entire set of B(I)'s, where B(I) is the number of bits of the I-th type. A partial structure is formed in which B(I)/M of each I-th bit type is provided. The number M identical integrated circuits of this partial structure are formed. Lastly, these identical integrated circuits are interconnected to form the whole structure desired.

Abstract: The present invention relates to a self testing data processing system which includes a communications bus enabling communication between nonintelligent data processing circuits and a plurality of intelligent data processing circuits. The communications bus has connection slots, each connection slot having a unique electrically readable slot number. Each data processing circuit connects to the communications bus via one of the connection slots. Each data processing circuit has an identity memory which indicates whether or not that circuit can be a system test master. In addition, all intelligent data processing circuits include within their identity memory an indication of whether or not they have passed a circuit self test. Upon initial application of electric power or upon system reset, each intelligent data processing circuit performs a circuit self test and then sets the identity memory to indicate whether or not they have passed this self test.

Abstract: The present invention relates to a self testing data processing system which includes a communications bus for communication between a number of slots, at least one nonintelligent data processing circuit connected to one of those slots and at least one intelligent data processing circuit connected to another of those slots. Each nonintelligent data processing circuit includes a test memory which is readable from the communication bus. The test memory has a diagnostic program stored therein for testing that nonintelligent data processing circuit. This diagnostic program is written in an intermediate level interpretable test language. Each of the intelligent data processing circuits includes an interpreter program for interpreting the intermediate level interpretable test language into the native code of the intelligent data processing circuit.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. For a given set of addresses parallel data transfers occur and for a different set of addresses serial data transfers occur. A single instruction may transfer one bit, multiple bits in series, or bytes or words in parallel; the serial or parallel mode is specified by the address, so software may be written without regard for the type of interface. This serial/parallel I/O port shares the address/data bus with memory and may be used with any memory-mapped peripheral.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. The control ROM is an array of rows and columns of potential MOS transistors. This ROM is compressed by eliminating column lines which contain no transistors, and eliminating column decode circuitry associated with such column lines. The number of lines which can be eliminated is increased by reducing the number of row lines (thereby lengthening the row lines) and selecting default conditions of controls (by inverting some outputs) to increase the number of vacant positions in the ROM.