Abstract: A method of modulating data, which is represented by two data types of ‘high’ and ‘low’, and demodulating the modulated data, is disclosed. In a method of data modulation and demodulation for a communication system which has a transmitting end modulating a data and a receiving end demodulating the transmitted data from the transmitting end, the data is represented by two types including ‘high’ and ‘low’, and the receiving end receives at least one data which consists of at least one code-word spread by a unique orthogonal code. The receiving end adds up the received data in the unit of code-word, and subtracts the length of the orthogonal code from a value which is obtained by doubling the sum of the code-word, when the code-word of the orthogonal code is ‘0’. The receiving end then averages the result after the subtraction in the unit of orthogonal code length and extracts the result, and therefore, obtains the data from the transmitting end.

Abstract: A method of modulating data, which is represented by two data types of ‘high’ and ‘low’, and demodulating the modulated data, is disclosed. In a method of data modulation and demodulation for a communication system which has a transmitting end modulating a data and a receiving end demodulating the transmitted data from the transmitting end, the data is represented by two types including ‘high’ and ‘low’, and the receiving end receives at least one data which consists of at least one code-word spread by a unique orthogonal code. The receiving end adds up the received data in the unit of code-word, and subtracts the length of the orthogonal code from a value which is obtained by doubling the sum of the code-word, when the code-word of the orthogonal code is ‘0’. The receiving end then averages the result after the subtraction in the unit of orthogonal code length and extracts the result, and therefore, obtains the data from the transmitting end.

Abstract: A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Abstract: An input buffer device and control method of the input buffer device. The input buffer device includes a virtual output queuing (VOQ) buffering section which has a plurality of VOQ buffers. The input buffer device stores data which is input to an input port to a VOQ buffer corresponding to an intended output port of the data among the plurality of VOQ buffers. A shared buffering section is provided which stores the data when a VOQ buffer corresponding to the intended output port of the data is full of data. The stored data is forwarded to the VOQ buffer when the VOQ buffer is empty. Accordingly, the input buffer device can more efficiently process the data by use of the fixed-length FIFO buffers and the shared buffer.

Abstract: A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A NULL convention full adder receives a plurality of inputs, each having an asserted state and a NULL state. The adder switches its output to an asserted state when all inputs have been received and summed. The adder switches its output to the NULL state only after all inputs have returned to NULL. A register can be incorporated into each full adder. Multiple full adders are combined into multi-bit adders with registration.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A digital signal processor including a digital FIR filter and memory for storing filter coefficients operates at a reduced power level by using array multipliers that calculate partial products only when the partial products in a preceding row of the array have stabilized. The dynamic CMOS adder arrays in each multiplier are triggered to perform their evaluations only after predetermined time periods have elapsed, which are sufficient to permit the preceding row to stabilize. Coefficients are addressed from the memory using low-power addressing circuits, such as a Gray code counter or a one-bit wide circular shift register, so that the overall digital signal processor consumes a reduced amount of power during memory addressing.