Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimizied. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted.

Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted.

Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted.

Abstract: The disclosure relates to demotion of data to a backing store (disk storage apparatus--DASD) from a random access cache in a peripheral data storage system. A cache replacement control list, such as a least recently used (LRU) list is scanned in a soon-to-be replaced first portion (portion closest to LRU entry) to identify first data to be demoted. Then the control list is scanned in first and second portions to identify further data to be demoted with the first data as a single group of data. In DASD, such data is all storable in the same cylinder of the DASD.

Abstract: In a multiunit data processing system, such as a multicontrol unit peripheral data storage system, a least busy one of the units requests work to be done from a busier unit. The busier unit, a work sending unit, supplies work to the work requesting or least busy unit. Work thresholds in the respective units determine when work is to be requested or transferred. In a data storage environment, the transferred work consists of data transfers to be achieved usually asynchronously to connected host activities, such as data transfers between a backing and a front store in a data storage hierarchy.

Abstract: In a data storage system employing sequential data transfers for blocks of data bytes, an address offset is induced in the addressing mechanism such that each block transfer requires loading the address mechanism with an address of a block to be accessed. Address offset is preferably induced by inserting a blank register between adjacent blocks.

Abstract: A plurality of addressable data storage devices are selectively directly accessed or accessed via a cache memory. Access via the cache memory uses one of a plurality of logical addresses; each of the data storage devices is represented by a plurality of the logical addresses. Each of the data storage devices can be reserved for direct access; such reservation does not apply to device accesses via the cache. Accesses to the devices are queued on a device basis.

Abstract: A two-level storage system selectively enables early discard of data from an upper level either immediately or at the end of a predetermined sequence of operation. A copy of data in such upper level is discarded immediately while altered copies of data are discarded at the end of the predetermined sequence of operations. Error conditions inhibit discarding altered data.

Abstract: Direct access storage devices (DASD) are connected to a host via a cache. Each device can be independently addressed by any one of a plurality of addresses, also termed logical devices and exposures. Since operations between DASD and cache are combined for all of the independent logical devices, resetting operations related to one independent logical device can inadvertently interfere with operations of another independent logical device. To maintain data integrity, a programmed control accommodates logical device independence by using queues and control blocks relating to the DASD and logical devices, respectively.