Abstract: Accordingly, the present invention provides a method for synchronously accessing memory in order to improve the performance in systems which use memories with slower cores. A first address for a first memory access is provided during a first clock period. A first control signal to indicate an address phase of the first memory access is activated during the first clock period. A second control signal to indicate a data phase of the first memory access is activated during a second clock period subsequent to the first clock period. A first data element accessed by the first address is received during a third clock period immediately subsequent to the second clock period. A second address for a second memory access is provided during the third clock period. The first control signal indicating an address phase of the second memory access is activated during the third clock period.

Abstract: An integrated circuit microprocessor (30) reads data from an external memory device (22, 23) through early overlapping memory access cycles, thus allowing efficient accesses to slower-speed memory. The microprocessor (30) drives a first address and activates a chip enable signal during a first clock period. The chip enable signal causes the external memory device to latch the first address and begin a first memory access. During a second, subsequent clock period, the microprocessor (30) provides a second address and again activates the chip enable signal. During a third clock period, subsequent to the second clock period, the microprocessor (30) latches a first data element associated with the first address. This early overlapping memory access type allows a memory device with a slow memory core to pipeline the second access prior to completion of the first access, increasing system efficiency.