Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Abstract: An m-of-n threshold gate is disclosed having an output stated derived from the voltage of a signal node. A “Go-to-Data” circuit pulls the signal node to a first state, corresponding to an ASSERTED (logically meaningful) output when a threshold number of inputs is in the ASSERTED state. A “Go-to-NULL” circuit pulls the signal node to a second state, corresponding to a NULL (logically meaningless) output when all inputs are in the NULL state. In a semi-dynamic embodiment, a weak feedback transistor holds the signal node in a predetermined state when some, but less than the threshold number of inputs is ASSERTED. In a dynamic embodiment, the signal node becomes isolated when less than the threshold number of inputs is ASSERTED, but holds sufficient charge to maintain the signal node in a state that existed at the time of isolation. A variety of GTN circuits are disclosed.

Abstract: Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic meaning. Threshold values may be equal to or less than the number of input signal lines. Threshold gates switch their outputs from NULL to a meaningful state when the threshold number of inputs assume meaningful states. Gates will hold outputs in a meaningful (or non-null) state when the number of asserted inputs remains positive, even if the number is less than the threshold. In one embodiment, threshold gates include a "FLASH" input that forces the gate to NULL. In another embodiment, threshold gates include one or more "SET" inputs that drive the gate output to NULL or to a meaningfull state.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.