Patents by Inventor Gerald H. Johnson

Gerald H. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9164158
    Abstract: An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: October 20, 2015
    Assignee: Teradyne, Inc.
    Inventors: Gerald H. Johnson, Babak Nikoomanesh, Chiyi Jin, Wolfgang Maichen
  • Publication number: 20140361798
    Abstract: An example apparatus is for use in calibration of a test system having multiple channels and a socket for receiving a device under test. The example apparatus includes a device interface that is connectable to the socket; and multiple circuit paths, where each circuit path is connectable, through the device interface, to a corresponding channel of the test system and being connected to a common node. The example apparatus is configured so that, during calibration, signals either (i) each pass from the test system, through one of the multiple circuit paths, and back to the test system through others of the multiple circuit paths, or (ii) each pass from the test system, through the others of the multiple circuit paths, and back to the test system through the one of the multiple circuit paths.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventors: Gerald H. Johnson, Babak Nikoomanesh, Chiyi Jin, Wolfgang Maichen
  • Patent number: 8373432
    Abstract: Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: February 12, 2013
    Assignee: Teradyne Inc.
    Inventor: Gerald H. Johnson
  • Publication number: 20100259277
    Abstract: Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT.
    Type: Application
    Filed: March 16, 2010
    Publication date: October 14, 2010
    Applicant: TERADYNE, INC.
    Inventor: Gerald H. Johnson
  • Patent number: 7085668
    Abstract: A time measurement circuit includes N time stamping units that each includes a dual sinusoid interpolator for achieving high timing resolution. The time measurement circuit is capable of time stamping input signals at a high re-trigger rate, and is thus well suited for quickly measuring the timing jitter of test signals in automatic test systems.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: August 1, 2006
    Assignee: Teradyne, Inc.
    Inventor: Gerald H. Johnson
  • Patent number: 6916990
    Abstract: In one embodiment a high power interface apparatus is provided having a multilayer laminated cable including force conductor planes having flush and recessed portions and return conductor planes having flush and recessed portions. The flush portions of the conductor planes extend to a contact end of the laminated cable and the recessed portions are removed from the contact end. The flush portions are aligned along axes at the contact end. The flush portions of the return conductor planes are aligned at the contact end along axes aligned within recessed portions of the force conductor planes. A dielectric material separates the force and return conductor planes. Surface contact pads may be provided on the contact end including force contact pads, each contacting and extending along aligned flush portions of the force conductor planes, and including return conductor pads, each contacting and extending along aligned flush portions of the return conductor planes.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 12, 2005
    Assignee: Teradyne, Inc.
    Inventors: Arash Behziz, Frank Parrish, Donald Thompson, Arthur LeColst, Keith Breinlinger, Brian Brecht, Gerald H. Johnson
  • Patent number: 6906578
    Abstract: A control loop circuit is disclosed for optimizing a power supply output under varying load conditions. The power supplye has a main loop amplifier and an output stage to generate the output. The control loop circuit includes a static control path coupled to the output and having an error amplifier. The error amplifier is operative to generate an error signal for presentation to the main loop amplifier where the error signal represents the difference between a desired output and a sensed output. A dynamic control path is coupled to the error amplifier output and is responsive to the error signal to generate a dynamic compensation signal. The dynamic control path has an output coupled to the main loop amplifier output.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: June 14, 2005
    Assignee: Teradyne, Inc.
    Inventor: Gerald H. Johnson
  • Patent number: 6756807
    Abstract: A modular power supply architecture for automatic test equipment is disclosed. The power supply architecture includes a control module having a control signal output line and a plurality of output modules. The control module includes control circuitry to generate a control signal along the control signal output line and measurement circuitry coupled to the control signal output line. The output modules have respective control inputs coupled in parallel to the control signal output line to receive the control signal and respective current outputs connected in parallel. The output modules are operative in response to the control signal to generate respective currents at the current outputs. A current output bus receives and sums the respective current outputs, the output bus being isolated from the control signal line.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: June 29, 2004
    Assignee: Teradyne, Inc.
    Inventors: Gerald H. Johnson, Michael F. Taylor
  • Publication number: 20040060725
    Abstract: In one embodiment a high power interface apparatus is provided having a multilayer laminated cable including force conductor planes having flush and recessed portions and return conductor planes having flush and recessed portions. The flush portions of the conductor planes extend to a contact end of the laminated cable and the recessed portions are removed from the contact end. The flush portions are aligned along axes at the contact end. The flush portions of the return conductor planes are aligned at the contact end along axes aligned within recessed portions of the force conductor planes. A dielectric material separates the force and return conductor planes. Surface contact pads may be provided on the contact end including force contact pads, each contacting and extending along aligned flush portions of the force conductor planes, and including return conductor pads, each contacting and extending along aligned flush portions of the return conductor planes.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Arash Behziz, Frank Parrish, Donald Thompson, Arthur LeColst, Keith Breinlinger, Brian Brecht, Gerald H. Johnson
  • Publication number: 20030102870
    Abstract: A modular power supply architecture for automatic test equipment is disclosed. The power supply architecture includes a control module having a control signal output line and a plurality of output modules. The control module includes control circuitry to generate a control signal along the control signal output line and measurement circuitry coupled to the control signal output line. The output modules have respective control inputs coupled in parallel to the control signal output line to receive the control signal and respective current outputs connected in parallel. The output modules are operative in response to the control signal to generate respective currents at the current outputs. A current output bus receives and sums the respective current outputs, the output bus being isolated from the control signal line.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Gerald H. Johnson, Michael F. Taylor
  • Publication number: 20030080771
    Abstract: A control loop circuit is disclosed for optimizing a power supply output under varying load conditions. The power supplye has a main loop amplifier and an output stage to generate the output. The control loop circuit includes a static control path coupled to the output and having an error amplifier. The error amplifier is operative to generate an error signal for presentation to the main loop amplifier where the error signal represents the difference between a desired output and a sensed output. A dynamic control path is coupled to the error amplifier output and is responsive to the error signal to generate a dynamic compensation signal. The dynamic control path has an output coupled to the main loop amplifier output.
    Type: Application
    Filed: October 30, 2001
    Publication date: May 1, 2003
    Inventor: Gerald H. Johnson
  • Patent number: 6556034
    Abstract: A power supply is disclosed for use with a device-under-test disposed on a device board. The power supply includes a high-accuracy remote supply circuit including respective force and sense lines and a high-speed local supply circuit. The local supply circuit includes an active boost circuit having respective boost and sense lines coupled to the force and sense lines. The active boost circuit is operative to selectively cooperate with the remote supply circuit and, when the device-under-test demands a large dynamic current, provide the dynamic current until the remote supply circuit responds to the current demand.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: April 29, 2003
    Assignee: Teradyne, Inc.
    Inventors: Gerald H. Johnson, Michael F. Taylor
  • Patent number: 6504395
    Abstract: A power supply circuit is disclosed for use with a semiconductor tester to power a device-under-test. The power supply includes power generation circuitry disposed in the tester to generate power for the device-under-test. Load circuitry is disposed within the tester and coupled to the power generation circuitry to selectively simulate the electrical loading of a device-under-test on the power supply.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: January 7, 2003
    Assignee: Teradyne, Inc.
    Inventor: Gerald H. Johnson
  • Patent number: 5052537
    Abstract: A rotary travel limit stop apparatus having a first rotary member (10) and second and third independently rotatable members (14 and 20) having slightly different numbers of gear teeth which engage the gear teeth on a first member (10) carry a movable stop pin (30) which is adapted to engage a fixed stop member (40) only during a revolution near the limit stop position of a controlled element such as an aileron. A stop plate (54) carrying a fixed stop member (40) is angularly adjusted by rotation of a screw (70) which is received by a barrel nut (64) that is coupled to the stop plate (54) by a protuberance (66).
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: October 1, 1991
    Assignee: Sundstrand Corporation
    Inventors: John D. Tysver, Gerald H. Johnson
  • Patent number: 4882729
    Abstract: A paging controller for a paging communication system exchanges information by a global multiplexed bus arrangement. The bus arrangement permits voice, data and control information to be exchanged between a common memory and a plurality of I/O modules in a common communication bus. The timing signals of the bus arrangement including the I/O modules are synchronized to expeditiously exchange information among the modules. In operation, each module has a preassigned address representative of a sequence number in a predetermined succession order to permit each module to access the bus.
    Type: Grant
    Filed: August 7, 1988
    Date of Patent: November 21, 1989
    Assignee: Motorola, Inc.
    Inventors: Gary S. Lobel, Steven J. Goldberg, Gerald H. Johnson, Jr.
  • Patent number: 4546269
    Abstract: In a first searching mode of the control program for the microprocessor, the microprocessor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point which is intermediate to the minimum and maximum delay points. The microprocessor then, at each pass of the control program, successively increments the delay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated circuit fails, to indicate the late clocking failure limit. In the second searching mode of the microprocessor control program, the microprocessor starts at the late clocking failure limit and at each subsequent pass of the program successively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the semiconductor device fails again, to indicate the early clocking failure limit.
    Type: Grant
    Filed: December 1, 1983
    Date of Patent: October 8, 1985
    Assignee: Control Data Corporation
    Inventor: Gerald H. Johnson