Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: In a data processing system in which an extender unit interconnects the parallel bus of a control unit and a serial link of an extender channel, the channel and the extender unit send and receive serial frames that permit the extender unit to operate under the protocol of the parallel bus with either byte mode devices or non-byte mode devices. The control unit can be modified to operate with a byte mode device in data streaming, a high speed data transfer mode.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: A device control unit operating under the protocol of a parallel bus is connected by a serial link to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit interconnects the parallel bus and the serial link and performs the specific operations of the parallel bus protocol. The channel and the extender unit send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features.

Abstract: An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers in alternating fashion with frame contents bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the frame contents bytes from the selected input buffer to one of a pair of output buffers en route to the control unit. Upon detecting the receipt of the third incoming frame contents byte, the first state machine sets a start latch, causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled.

Abstract: A system for bit character synchronization of an 8/10 bit code being deserialized is provided by a deserializer with a skip bit function input used to move a character boundary one bit at a time, and 8/10 code error detector, a zero disparity character detector and skip pulse generator. After character sychronism is lost, the skip pulse generator is permitted to generate a skip pulse if the following sequence occurs: all bits of the old character boundary have been flushed through the logic circuits, at least one non-zero disparity character has been detected, and an 8/10 code error is detected. After character synchronism is re-acquired, then the skip pulse generator is no longer permitted to generate a skip pulse.

Abstract: Data is transferred between a channel and a control unit in interlocked mode or in data streaming mode over a conventional parallel bus and a serial link that permits the control unit and the channel to be located farther apart than the length of the parallel bus. The serial link carries frames for the rise of the data transfer tags but not their fall, and these tags on the parallel bus are dropped by two circuits that connect the serial link to the parallel bus. In data streaming mode, one data transfer tag is dropped when the next data transfer tag is received on the serial link. The circuit at the control unit end of the serial link detects a pause in the tags to begin an operation to drop the last data transfer tags and both circuits respond to other conditions to drop the last data transfer tags according to the protocol of the parallel bus.