Abstract: A pipelined parallel vector processor is disclosed. In order to increase the performance of the parallel vector processor, the present invention decreases the time required to process a pair of vectors stored in a pair of vector registers. The vector registers are subdivided into a plurality of smaller registers. A vector, stored in a vector register, comprises N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. An element processor, functioning in a pipeline mode, is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and generating results of the processing, the results being stored in one of the vector registers. The smaller registers of the vector registers, and their corresponding element processors, are structurally configured in a parallel fashion. The element processors and their associated smaller registers operate simultaneously.

Abstract: A pipelined paralled vector processor decreases the time required to process the elements of a single vector stored in a vector register. Each vector register of a plurality of vector registers is subdivided into a plurality of smaller registers. A vector, stored in a vector register, includes N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. A pipelined element processor is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and storing a result of the processing in a result register. Each of the smaller registers of the vector registers, and its corresponding element processor, comprise a unit. A plurality of units are connected in a parallel configuration. The element processors, associated with each unit, have been loaded with the result, the result being stored in a result register.

Abstract: A parallel vector processor includes a plurality of vector registers, each vector register being subdivided into a plurality of smaller registers. A vector is stored in each vector register, the vector has a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers.

Abstract: A method is provided for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

Abstract: A latch circuit possesses a scan capability, has a single clock input line, and possesses a locking feature whereby input data, once locked in the latch, is insensitive to further changes in state of the input data. The latch also possesses a novel selection apparatus which functions to select either a scan data input line or a system data input line in accordance with the binary state of a system gate input line, the selection apparatus developing an output signal, the binary state of which is locked in the latch in response to a predetermined state of a clock pulse conducted via the single clock line. Clock skew compensation is provided via the locking feature. During a scan mode, clock skew compensation is provided when the clock pulse is received for a period of time after termination of reception of a scan pulse conducted via the system gate input line.

Abstract: In a computer system, an instruction is executed. The results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. This information is used by the computer system during the execution of subsequent instructions. The results of the execution of the instruction comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction.