Abstract: Memory circuitry 2 includes a memory cell 12 coupled to a plurality of bit line pairs 18, 24 providing multiple access ports. Write boost circuitry 36 serves to increase a write voltage applied to write a data value into the memory cell during at least a boost period of a write access. Collision detection circuitry 10 detects when the write access at least partially overlaps in time with a read access. If a collision is detected, then write assist circuitry serves to drive the bit line pair of the detected read access with a write assist voltage difference having the same polarity as the write voltage and a magnitude less than the write voltage with the boost voltage applied. The write assist circuitry drives the bit line pair of the colliding read independently of the write boost circuitry applying the boost voltage such that the boost voltage is undiminished by the action of the write assist circuitry.

Abstract: Memory circuitry 2 includes a memory cell 12 coupled to a plurality of bit line pairs 18, 24 providing multiple access ports. Write boost circuitry 36 serves to increase a write voltage applied to write a data value into the memory cell during at least a boost period of a write access. Collision detection circuitry 10 detects when the write access at least partially overlaps in time with a read access. If a collision is detected, then write assist circuitry serves to drive the bit line pair of the detected read access with a write assist voltage difference having the same polarity as the write voltage and a magnitude less than the write voltage with the boost voltage applied. The write assist circuitry drives the bit line pair of the colliding read independently of the write boost circuitry applying the boost voltage such that the boost voltage is undiminished by the action of the write assist circuitry.

Abstract: A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations.

Abstract: A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations.