Abstract: A portable transceiver with a transmit/receive switch which includes an audio amplifier, level detector and comparator all direct coupled and included on a single integrated chip. The comparator includes one input that has a slow attack time and a fast decay time for differentiating between slow changing background noise and fast bursts of voice so that the transceiver is voice operated.

Abstract: A television receiver including a MPU and OSD circuitry on a single chip. The OSD circuitry includes multisystem detection circuitry which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL to synchronize the receiver to the received standard. The PLL includes a VCO having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector, which alternating phases cause jitter in the display.

Abstract: In a TV receiver including multistandard OSD circuitry a method and apparatus for positioning the display including a comparator which compares a predetermined count (position) with a count of the received horizontal frequency to provide delayed horizontal flyback pulses and a dot and column address generator which is synchronized to start with the delayed horizontal flyback pulses. Similar vertical positioning circuits are included.

Abstract: A TV receiver including a microprocessor and an on screen display on a single semiconductor chip. The OSD includes half dot logic and shifting to smooth the characters with a minimum of storage capacity required and the half dot logic is used in an edge enhancing circuit to generate a black surround. A simplified window generator is combined therewith to further improve the characters.

Abstract: A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.

Abstract: In a T.V. integrator circuit which separates vertical and horizontal synchronization pulses, the time constants thereof are set by extracting from the integrator a current representative of a reference current which is used to trim an associated horizontal oscillator. Current mirror circuits are used to both generate the representative signal at the horizontal oscillator and to extract the representative signal at the integrator.

Abstract: A circuit having a variable input impedance which is controlled by application of a direct current input signal. The variable impedance circuit comprises a pair of capacitors coupled in series with a pair of diodes. The diodes are rendered conductive in response to the direct current control signal to substantially short the two capacitors in series with one another across the input terminals of the circuit. With no direct control signal being applied to the circuit the diodes are non-conductive which substantially disconnects the capacitors from appearing across the inputs of the circuit. Hence, the reactance component of the input impedance of the circuit is varied in response to the direct control signal.

Abstract: A single chip integrated circuit that performs the electronic functions of a monochrome television receiver with the exception of the RF tuner, sound channel, and power output stages. The circuit includes video IF/detector and video processing as well as a two loop horizontal phase locked loop for locking the horizontal flyback to the horizontal sync pulses. In addition, a vertical processing stage is related to the horizontal sync pulses, is included for producing vertical flyback. The circuit operates in a vertical narrow window mode when coincidence occurs between the vertical sync pulses and the output of a vertical countdown circuit to thereby reduce interference from noise and operates in a wide window mode when vertical sync pulses are lost or not yet acquired to allow fast acquisition of the vertical sync pulses.

Abstract: A horizontal phase lock loop for use in a television receiver comprises first and second loops and a horizontal oscillator which generates a ramp signal at a frequency of twice the line frequency. The first loop locks the oscillator signal to the horizontal synchronization pulses. The oscillator output is sliced and then divided by two to achieve a fifty percent duty cycle drive waveform to the phase detector in the first loop and to a phase detector in the second loop. The second loop includes a variable slicer which operates on the oscillator ramp signal so as to lock the flyback signal generated by the horizontal output stage to the second phase detector's switching waveform. Both loops include a divide-by-two circuit which assures fifty percent duty cycle drive waveforms.

Abstract: A circuit and method for producing a signal that is nearly a perfect full wave rectified version of an applied alternating signal. The circuit comprises first and second identical non-linear symmetrical rectifiers each having a respective output coupled to a current mirror circuit. In response to the alternating signal being applied to the input of the first rectifier a full wave rectified signal is produced at the output thereof to drive the current mirror such that at the output thereof, which is coupled to the output of the second rectifier, there appears a signal identical to the output from the first rectifier. This signal is utilized to produce an input signal to the second rectifier to constrain the output signal therefrom to be identical to the output signal from the current mirror circuit. The input signal to the second rectifier is thus a perfect full wave rectified version of the input signal applied to the first rectifier.