Abstract: A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.

Abstract: A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.

Abstract: A method and circuit for flattening the output resistance response on a signal pad of an integrated circuit is presented. Impedance matching is accomplished using pull-up and pull-down FET arrays. Various combinations of pull-up PFETs in the pull-up FET array are programmably enabled by a pull-up calibration word when driving the output pad high. Various combinations of pull-down NFETs in the pull-down FET array are programmably enabled by a pull-down calibration word when driving the output pad low. An NFET in the pull-up FET calibration array and a PFET in the pull-down FET array respectively allow the output driver to supply more current during the initial stages of a voltage transition, resulting in a flatter overall output resistance Ro response.

Abstract: The present invention is generally directed to a PVT compensated variable impedance output driver for driving a signal through a signal pad on a semiconductor device. In accordance with one aspect of the present invention, the output driver includes a plurality of p-channel field effect transistors (PFETs) electrically connected in parallel. A source node of each of the plurality of PFETs are electrically connected together, and a drain node of each of the plurality of PFETs are electrically connected together. The driver further includes a plurality of n-channel field effect transistors (NFETs) electrically connected in parallel. A source node of each of the plurality of NFETs are electrically connected together and a drain node of each of the plurality of NFETs are electrically connected together.

Abstract: A circuit for matching the impedance of a first array of transistors to an external resistor is used to produce a first set of control signals. This first set of control signals is used to control another array of transistors to replicate the impedance of the first array of transistors. This replicated impedance is then used by another circuit for matching impedance to produce a second set of control signals that control an array of transistor of a different type to match the impedance of the first two array. The two sets of control signals may then be used as calibration signals for the pull-up and pull-down transistors of multiple output drivers.