Abstract: Methods, apparatuses, and computer readable media for utilizing a single model of event-based energies at multiple hierarchical levels of a design. The event-based energy model contains multiple interfaces that access or reference lower level power data, such as pin-based power data. The power of a transaction level definition of a design is estimated using the event-based energy model. The transaction-level definition of the design uses indirect references to access the event-based energy model. Other abstraction levels of the design may have their power estimated using the same low-level event-based energy model. Overall, a consistent power estimation of a design is performed using the same event-based energy model at different levels of abstraction of the design flow.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A method and a design automation tool are provided for use in conjunction with designing logic circuits that implement virtual power signals. The method includes providing in a model for each virtual power signal an attribute that distinguishes the virtual power signal from both a logic signal and a power signal. The method also includes one or more circuit analysis, processing and synthesis tool that takes advantage of such an attribute. That is, within the design automation tool, capabilities are provided so that a virtual power signal may be processed in some instances as a logic signal, and at some instance as indistinguishable to a power rail signal or reference.

Abstract: A tool and a method analyze variations in signal timing, especially timing in a clock signal, commonly known as “clock Jitter.” The tool and method provide advantages over conventional analysis approaches, such as comprehensive coverage of all clocks in a design, taking into account all signal coupling effects, ease of use, ability to automatically identify individual jitter sources, and efficient use of computing resources.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.

Abstract: A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these standard cells may be provided by the switch cells or by specialized tap cells. The tapless standard cells may include only a context-sensitive rail, which may be configured to be a virtual ground rail by a power gating connection to a switch cell or by a direct connection to a power supply or ground rail.

Abstract: A current waveform for an electronic circuit is calculated from a description of the circuit at a given level of abstraction without requiring a detailed simulation. In one embodiment, the waveform is estimated without using test vectors, and uses an analysis time step or “granularity” that is much shorter than a clock cycle. The method is applicable for calculating worst-case instantaneous current.

Abstract: This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that only temporally mutually exclusive currents, or currents whose cumulative sum is less than a predetermined value, can flow in any given switch cell. Techniques for current event merging and current event culling, and techniques for handling timing and current variances may be used.

Abstract: A current waveform for an electronic circuit is calculated from a description of the circuit at a given level of abstraction without requiring a detailed simulation. In one embodiment, the waveform is estimated without using test vectors, and uses an analysis time step or “granularity” that is much shorter than a clock cycle. The method is applicable for calculating worst-case instantaneous current.

Abstract: A method and apparatus is described which enables a user to analyze an electrical design utilizing a computer. The elements of the electrical design are described at a register transfer level. Embodiments of the invention are described which allow the user to enter the elements described at the register transfer level and estimate the power consumption of portions or all of the electrical design.

Abstract: The disclosure concerns asynchronous to synchronous synchronizers and particularly a technique which involves level shifting of a metastable voltage either within a synchronizer stage or between synchronizer stages. In a particular implementation of the invention, this level shifting is achieved by altering the relative proportions of at least one complementary pair of devices in a synchronizer or inserting diodes in order to shift the level of a metastable voltage outside the range of a fatal voltage window possessed or exhibited by an adjacent or following part or stage of the synchronizer. By this means, although the occurrence of a metastable condition cannot be avoided, the likelihood of propagation of the metastable condition throughout the synchronizer may be very significantly reduced.

Abstract: A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh cycle at the beginning of a clock cycle. Immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.

Abstract: A testable power-on-reset circuit allows the reset of an electronic device without de-coupling a power signal from the electronic device. The testable power-on-reset circuit includes reset circuitry, a buffer and a buffer controller. The reset circuitry includes a reset power line on which is placed a reset power signal. The reset circuitry also includes a reset output upon which the reset circuitry places a first reset signal value responsive to the reset circuitry initially detecting the reset power signal on the reset power line and upon which the reset circuitry places a second reset signal value responsive to a period of time passing from the reset circuitry initially detecting the reset power signal on the reset power line. When it is desired to test the reset of the electronic device, the buffer controller, in response to a predetermined condition, causes the buffer to remove the reset power signal from the reset power line of the reset circuitry.