Abstract: A computer storage system having a dual port buffer memory for improved performance. The invention comprises a computer storage subsystem that includes a dual port buffer memory that effectively provides two internal data busses for the storage subsystem: one bus for data transfers between the dual port buffer memory and the storage units, and a second bus for data transfers between the dual port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. In alternative configurations, the invention may use a plurality of dual port buffer memories in parallel to increase the effective throughput of the storage subsystem, and better match the bandwidth of the two busses.

Abstract: An environment sensing/control circuit for use in conjunction with an electronic subsystem. The invention is capable of sensing and controlling conditions of the environment of the subsystem. The invention is capable of being implemented as a stand-alone device or replicated numerous times in an integrated circuit. The invention identifies changes including intermittent changes, in the environment of the subsystem from a reference state, the reference state being dynamically determined by a processor. Upon detecting such a change, the invention signals the processor. The invention can also serve as a flexible interface for control signals from the processor to the subsystem.

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO.