Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Abstract: Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Abstract: Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.