Patents by Inventor Gerald Lepage

Gerald Lepage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8207485
    Abstract: A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: June 26, 2012
    Assignee: On Semiconductor Image Sensor
    Inventor: Gerald LePage
  • Patent number: 7675561
    Abstract: A time delayed integration image sensor provides over-sampled image data on a time-shared column bus to maintain data synchronization.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: March 9, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventor: Gerald Lepage
  • Publication number: 20090230289
    Abstract: A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node.
    Type: Application
    Filed: May 28, 2009
    Publication date: September 17, 2009
    Applicant: Cypress Semiconductor Corporation
    Inventor: Gerald LePage
  • Publication number: 20080079830
    Abstract: A time delayed integration image sensor provides over-sampled image data on a time-shared column bus to maintain data synchronization.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventor: Gerald Lepage
  • Patent number: 7333040
    Abstract: An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: February 19, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bart Dierickx, Gerald Lepage, Tomas Geurts