Abstract: The disclosed systems and methods relate to a reduction of system complexity by incorporating a clock cut-off signal in an SDIO device in order to support a multi-drop architecture. Aspects of the present invention enable a multi-drop architecture with an SDIO device and multiple SD memory devices sharing the same SD bus. Aspects of the present invention may also reduce host complexity by enabling a single host to control an SD device and multiple SD memory cards.

Abstract: The present invention is a method and system to minimize the timing errors introduced by the use of a sleep clock, utilized in timing a sleep period, for a mobile station. Further, the present invention restarts a high frequency reference clock after the sleep period with a zero mean time error to ensure that the receiver of the mobile station is properly synchronized with a base station for the receipt of pages. A low frequency sleep clock is calibrated with respect to a high frequency reference clock during a pre-defined calibration period. Based upon the calibration, a calibration error for the sleep clock is determined. Next, a wake-up time error is calculated, based upon the calibration error, to compensate for the error of the sleep clock. The wake-up time error compensates for the error of the sleep clock during the sleep period such that the reference clock restarts at the end of the sleep period with a zero mean time error.