Abstract: An auto-zeroing sample-hold amplifier capable of tracking an input voltage and, when designated, sampling and accurately holding an input voltage with no gain or offset errors includes input and output buffers with complementary, equal-magnitude offsets for minimizing offset voltage errors. An input voltage is sampled across a primary hold capacitor as well as a secondary hold capacitor [at the amplifier output to] in a sample mode. In a hold mode, the capacitors, in conjunction with the buffers and a transconductance amplifier, form a negative feedback loop around the transconductance amplifier to hold the sampled voltage and reduced voltage excursions at the output of the sample-hold amplifier. A special cancellation switch and capacitor are included for differentially cancelling voltage errors caused by switch charge feed-through onto the primary hold capacitor.

Abstract: A sample/hold amplifier comprising two transconductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mold, the roles of the two transconductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages.

Abstract: A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group.

Abstract: A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group.

Abstract: A dissipative-type muffler for attenuating the high velocity discharge of a high pressure-high temperature safety valve. A path of flow constituting four stages of controlled turbulence suppressed diffusion is formed internally of the muffler extending from an intake into a plenum chamber then distributed past a plurality of parallel arranged radial diffuser flanges and an acoustical liner before exiting to atmosphere at relatively low velocity and low noise level. Laminar flow to small scale turbulence is obtained in the first stage by a jet impingement directional reversal in a controlled spacing discharge from an intake pipe within the plenum chamber. In the second stage, small scale discharge turbulence of high frequency is achieved by laminar flow induced via radial diffusion through controlled gap spacings between the diffuser flanges.

Abstract: A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.

Abstract: A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor, to which this application is directed to, as the shunt feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.