Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Abstract: Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Abstract: Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Abstract: Systems and methods receive a design of a circuit layout. The circuit layout has some available spaces. Such systems and methods automatically insert capacitor arrays in the specified spaces. Each of the capacitor arrays has capacitor cells, and each of the capacitor cells has capacitor structures and a buried implant. The process of inserting the capacitor arrays comprises a process of forming the capacitor arrays to either: grow the capacitor arrays to the size of the specified spaces; grow the capacitor arrays to a specified capacitance value within the restriction of the length dimension or the width dimension of the specified spaces; or grow the capacitor arrays to a specified capacitance value, irrespective of dimensional length dimension or width dimension limitations (where the only limitations are the dimensions of the specified space).

Abstract: An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output.

Abstract: A method and system for rendering and filling non-complex polygon outlines using vertical span architecture. Three control planes are used to control the rendering and filling of pixels. These control planes include a fill control plane, which is filled with bits at locations corresponding to the first and last points of each vertical span of a polygon outline; an edge plane, which is filled with bits at locations corresponding to pixels having a center lying on an oblique edge of the polygon outline or having a center lying on a beginning or ending of each edge; and a Y direction plane, which is filled with bits indicating whether the edge is directed in a positive or negative Y direction at locations corresponding to the filled locations in the edge plane. The polygon is filled by proceeding along successive vertical spans, processing each span in accordance with the contents of the three control planes and the rendering orientation of the polygon outline.

Abstract: A method and system for generating an antialiased approximation of a line displayed within a data processing system having a raster-scan device for generating images within a two-dimensional grid comprising rows and columns of pixels. A plurality of parameters are generated according to Bresenham's algorithm for the line, including first error term and a second error term. A pixel intensity for an initial pixel for the pixel approximation of the line is generated. The first error term is compared with a threshold to determine an amount of error. The first error term is adjusted by a first selected amount in response to the comparison of the first error term, and the second error term is adjusted by a second selected amount in response to the comparison of the first error term. A pixel proximate to the initial pixel is selected by comparing the first adjusted error term with a second threshold to locate a pixel closest to a point on the line.