Abstract: A frequency correction apparatus having a delay line fed by an input signal, the frequency of such signal being corrected a predetermined amount, .DELTA.f. The delay line has a plurality of output taps regularly disposed along the line. The output taps produce a plurality of successively time-delayed signals each one having the frequency of the input signal. A switching network is included for successively coupling each one of the plurality of time-delayed signals to an output terminal of a predetermined coupling change rate related to .DELTA.f, to produce, at such output terminal, an output signal having a frequency shifted from the frequency of the input signal the predetermined amount required for the desired frequency correction. When the taps are successively coupled to the output terminal in a direction along the delay line away from the input to such line, the frequency of the output signal is equal to the frequency of the input shift shifted lower in frequency the amount .DELTA.f.

Abstract: A raster display apparatus for converting radar input data which is formatted to produce a Plan Position Indicator (PPI) presentation on a cursive display to a format which achieves a PPI type image on a raster display. The apparatus generates radar images on a raster display screen which appear as targets having continuous arcs of the proper length around the placement position of a radar. Average video levels within successive discrete fixed azimuthal standard angle increments are stored in a radial buffer memory for various increments of range. These video levels are used for all points within the presently active standard angular increment. Radial distance of a given image is computed for changes in orthogonal components such as X or Y using simple prestored sine and cosine functions. Conversion calculations comprise primarily additions using adders.

Abstract: Method and apparatus permitting a multi-module digital system, such as a puter, having built-in test hardware associated with each module, including a plurality of signal processing units to communicate over two wire circuitry not only the existence of a failure of a particular module, but also its causality. This is accomplished by means of a four state signaling circuit interposed between each signal processing unit of a particular module and a module built-in test circuit which operates once an error output is reported by a signal processing unit to provide a further four state indication of the details of the failure.

Abstract: A display system line generator network having an error correction feedback loop which achieves high positional accuracy for both plan position indicators PPI and synthetic character and line data. Digital reference position and relative beam motion data are fed into separate D/A converters. The staircase effect at the output of the D/A that processes the relative beam motion data is eliminated in a constant current integrator. The output of the integrator is combined with the reference position signal in a summing amplifier and the summed signal is fed to a deflection amplifier. A feedback circuit picks off the inputs to the summing amplifier and uses their comparison to synchronize time with beam position by compensating for errors due to component drift and aging.

Abstract: A system for the generation of a set of voltages, such as the X and Y coordinate voltages of a display or automated milling machine, includes a character generator and a character positioning circuit which, in turn, are responsive to digital control signals as are produced by a computer. A detector compares detection signals to reference signals at successive instants during the use of the system. The computer utilizes a learning routine in conjunction with voltage generation circuitry to develop the reference signals. The computer is programmed to provide specific values of the digital control signals at the times of the comparisons by the detector to detect any deviation of the magnitudes of the voltages of the deflection circuitry from the magnitudes attained during an initial alignment of the system.

Abstract: High accuracy function calculating apparatus using a minimum of components and storage locations. Second difference values of the function to be generated are stored in a read-only memory which is addressed by an incrementable and reversible address counter. A first accumulator circuit connected to the output of the read-only memory calculates the first difference values of the function. A second accumulator coupled to the output of the first accumulator calculates the values of the desired function. The apparatus is used to advantage in radar azimuth converter applications as well as in general purpose function calculating applications.

Abstract: High accuracy function calculating apparatus using a minimum of components and storage locations. Second difference values of the function to be generated are stored in a read-only memory which is addressed by an incrementable and reversible address counter. A first accumulator circuit connected to the output of the read-only memory calculates the first difference values of the function. A second accumulator coupled to the output of the first accumulator calculates the values of the desired function. The apparatus is used to advantage in radar azimuth converter applications as well as in general purpose function calculating applications.