Patents by Inventor Gerald Pasdast

Gerald Pasdast has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253233
    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
    Type: Application
    Filed: April 23, 2025
    Publication date: August 7, 2025
    Inventors: Adel ELSHERBINI, Mauro KOBRINSKY, Shawna LIFF, Johanna SWAN, Gerald PASDAST, Sathya Narasimman TIAGARAJ
  • Patent number: 12362284
    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
    Type: Grant
    Filed: April 5, 2024
    Date of Patent: July 15, 2025
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast
  • Patent number: 12362306
    Abstract: Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: July 15, 2025
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu, Swadesh Choudhary
  • Patent number: 12353305
    Abstract: In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Swadesh Choudhary, Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast
  • Patent number: 12332826
    Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan, Gerald Pasdast, Zuoguo Wu
  • Patent number: 12321305
    Abstract: In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 3, 2025
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Swadesh Choudhary, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Gerald Pasdast
  • Patent number: 12315794
    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Mauro Kobrinsky, Shawna Liff, Johanna Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj
  • Patent number: 12288746
    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 29, 2025
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Mauro Kobrinsky, Shawna Liff, Johanna Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj
  • Patent number: 12164319
    Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.
    Type: Grant
    Filed: December 19, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Sathya Narasimman Tiagaraj, Gerald Pasdast, Edward Burton
  • Patent number: 12159840
    Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Gerald Pasdast, Juan Zeng, Peipei Wang, Ahmad Siddiqui, Lakshmipriya Seshan
  • Publication number: 20240329129
    Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
    Type: Application
    Filed: December 12, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Sridhar Muthrasanallur, Debendra Das Sharma, Swadesh Choudhary, Gerald Pasdast, Peter Onufryk
  • Patent number: 12100662
    Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Gerald Pasdast, Peipei Wang, Daniel Krueger, Edward Burton
  • Publication number: 20240311330
    Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2023
    Publication date: September 19, 2024
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Narasimha Lanka, Peter Onufryk, Swadesh Choudhary, Gerald Pasdast, Zuoguo Wu, Dimitrios Ziakas, Sridhar Muthrasanallur
  • Publication number: 20240274542
    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
    Type: Application
    Filed: April 5, 2024
    Publication date: August 15, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast
  • Patent number: 12014990
    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast
  • Publication number: 20240183884
    Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Inventors: Vikrant Thigle, Vijay Anand Mathiyalagan, Anand Haridass, Arun Chandrasekhar, Gerald Pasdast
  • Patent number: 11899615
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • Patent number: 11749649
    Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Johanna Swan, Shawna Liff, Patrick Morrow, Gerald Pasdast, Van Le
  • Publication number: 20230258716
    Abstract: Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2023
    Publication date: August 17, 2023
    Applicant: Intel Corporation
    Inventors: Swadesh Choudhary, Debendra Das Sharma, Gerald Pasdast, Zuogo Wu, Narasimha Lanka, Lakshmipriya Seshan
  • Publication number: 20230245972
    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: INTEL CORPORATION
    Inventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast